{"id":153,"date":"2012-02-21T16:23:14","date_gmt":"2012-02-21T07:23:14","guid":{"rendered":"http:\/\/www.gvc-on.net\/?page_id=153"},"modified":"2014-01-21T14:52:35","modified_gmt":"2014-01-21T05:52:35","slug":"pic12f1822-data-io-by-i2c","status":"publish","type":"page","link":"https:\/\/www.gvc-on.net\/?page_id=153","title":{"rendered":"PIC(12F1822) DATA I\/O by I2C"},"content":{"rendered":"<p>PIC(12F1822)\u3092\u5229\u7528\u3057\u3066\u3001GVC(Arduino)\u3068I2C\u3067\u30c7\u30fc\u30bf\u306e\u3084\u308a\u53d6\u308a\u3092\u3059\u308b\u30b5\u30f3\u30d7\u30eb\u30bd\u30fc\u30b9\u3067\u3059\u3002<br \/>\n\u73fe\u5728\u7b56\u5b9a\u4e2d\u306eGVC\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u3067\u3001I2C\u306e\u30de\u30b9\u30bf\u30fc\u3067\u3042\u308bArduino\u304b\u3089\u3001\u30b9\u30ec\u30fc\u30d6\u3067\u3042\u308bPIC\u306b\u5bfe\u3057\u3066\u30c7\u30fc\u30bf\u3092\u8981\u6c42\u3057\u3066\u3044\u307e\u3059\u3002<br \/>\n\u53d7\u3051\u305fPIC\u306f\u30c7\u30fc\u30bf\u3092\u7528\u610f\u3057\u3066Arduino\u306b\u30c7\u30fc\u30bf\u3092\u8fd4\u3057\u307e\u3059\u3002(\u3053\u3053\u3067\u306f&#8217;A&#8217;,&#8217;B&#8217;,&#8217;C&#8217;,&#8217;D&#8217;\u306e4\u30d0\u30a4\u30c8)<\/p>\n<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\n\/\/ --------------------------------------------------\r\n\/\/ Global Versatile Controler\r\n\/\/ --------------------------------------------------\r\n\/\/ --------------------------------------------------\r\n\/\/ Memo\r\n\/\/ --------------------------------------------------\r\n\/\/ ------------------------------\r\n\/\/ 12F1822 I2C DATA IN\/OUT\r\n\/\/ ------------------------------\r\n\/\/ New BSD License. Copyright (c) 2011-2012, Future Versatile Group\r\n\/\/ All rights reserved.\r\n\/\/\r\n\/\/ 2011.12.16 T.Kabu\r\n\/\/\r\n\/\/ PIC\u3092I2C\u306e\u30b9\u30ec\u30fc\u30d6\u3068\u3057\u3066\u3001\u30de\u30b9\u30bf\u30fc\u3067\u3042\u308bGVC(Arduino)\u3068\u901a\u4fe1\u3092\u3059\u308b\u305f\u3081\u306e\u30b5\u30f3\u30d7\u30eb\u30bd\u30fc\u30b9\u3067\u3059\u3002\r\n\/\/ \u4ed6\u306ePIC\u3001\u307e\u305fPIC\u305d\u306e\u3082\u306e\u306e\u8a2d\u5b9a\u306b\u3088\u308a\u6319\u52d5\u304c\u7570\u306a\u308b\u5834\u5408\u304c\u3042\u308b\u306e\u3067\u6ce8\u610f\u3059\u308b\u3053\u3068\u3002\r\n\/\/\r\n\/\/ \u203b\u3053\u306e\u30bd\u30fc\u30b9\u306f\u30b5\u30f3\u30d7\u30eb\u3067\u3059\u3002GVC\u30d7\u30ed\u30c8\u30b3\u30eb\u306f\u73fe\u5728\u3082\u4ed5\u69d8\u7b56\u5b9a\u4e2d\u306a\u306e\u3067\u30bd\u30fc\u30b9\u304c\u5909\u66f4\u306b\u306a\u308b\u5834\u5408\u304c\u3042\u308a\u307e\u3059\u3002\r\n\r\n\/\/---------------------------------------------------\r\n\/\/ include\r\n\/\/---------------------------------------------------\r\n#include\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Const Define\r\n\/\/ --------------------------------------------------\r\n#define I2C_ADDR    0x20    \/\/ PIC\u306eI2C\u30a2\u30c9\u30ec\u30b9\u3001\u9069\u6642\u5909\u66f4\u3059\u308b\u3053\u3068\r\n#define RED_LED     RA5     \/\/ \u52d5\u4f5c\u78ba\u8a8d\u7528LED\u3092\u63a5\u7d9a\u3059\u308b\u30dd\u30fc\u30c8\r\n\r\n#define ON_LED      0;\r\n#define OFF_LED     1;\r\n\r\n\/\/ Delay\u7528\u306e\u5468\u6ce2\u6570\u5ba3\u8a00\u3002PIC\u305d\u306e\u3082\u306e\u306e\u5185\u90e8\u30af\u30ed\u30c3\u30afOSCCON\u3092\u5909\u66f4\u3057\u305f\u3089_XTAL_FREQ\u3082\u5909\u66f4\u3059\u308b\u3053\u3068\r\n#define _XTAL_FREQ  4000000    \/\/ 4MHz\r\n\r\n__CONFIG(\r\n    FOSC_INTOSC &amp; WDTE_OFF &amp; PWRTE_ON &amp; MCLRE_ON &amp; CP_OFF\r\n    &amp; CPD_OFF &amp; BOREN_OFF &amp; CLKOUTEN_ON &amp; IESO_OFF &amp; FCMEN_OFF\r\n);\r\n__CONFIG(\r\n    WRT_OFF &amp; PLLEN_OFF &amp; STVREN_ON &amp;  LVP_OFF\r\n);\r\n\r\n#define RX_BUFF_SIZE    8\r\n#define TX_BUFF_SIZE    8\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Variable Param\r\n\/\/ --------------------------------------------------\r\nunsigned char rx_buffer&#x5B;RX_BUFF_SIZE];    \/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\r\nunsigned char rx_count = 0;               \/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\r\n\r\nunsigned char tx_buffer&#x5B;TX_BUFF_SIZE];    \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\r\nunsigned char tx_count = 0;               \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\r\n\r\nstatic volatile char i2c_flag = 0;        \/\/ I2C\u53d7\u4fe1\u5b8c\u4e86\u30d5\u30e9\u30b0\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Sub Routine\r\n\/\/ --------------------------------------------------\r\n\/\/ ------------------------------\r\n\/\/ Delay 10m sec\r\n\/\/ ------------------------------\r\nvoid Delay_10ms(unsigned char time)\r\n{\r\n    \/\/ _XTAL_FREQ\u3068\u3044\u3046\u5b9a\u6570\u3092\u5ba3\u8a00\u3059\u308b\u3053\u3068\u3002PIC\u305d\u306e\u3082\u306e\u306e\u5185\u90e8\u30af\u30ed\u30c3\u30afOSCCON\u3092\u5909\u66f4\u3057\u305f\u3089_XTAL_FREQ\u3082\u5909\u66f4\u3059\u308b\u3053\u3068\r\n    \/\/ time\u30921\u6e1b\u3089\u3057\u3064\u306410ms\u5f85\u3064\u3002\u4f8b\uff1atime=100\u306a\u3089100x10ms=1000ms=1s\u5f85\u3064\r\n    while(time--)\r\n    {\r\n        __delay_ms(10);    \/\/ wait 10ms\r\n    }\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ LED Bright\r\n\/\/ ------------------------------\r\nvoid LED_Bright(char param1, char param2)\r\n{\r\n    \/\/ \u9577\u6642\u9593\u70b9\u706f\u30eb\u30fc\u30d7\r\n    while (param1 &gt; 0)\r\n    {\r\n        \/\/\u30e2\u30cb\u30bf\u30fcLED\u3092\u70b9\u706f\r\n        RED_LED = ON_LED;\r\n        Delay_10ms(50);\r\n        \/\/ \u30e2\u30cb\u30bf\u30fcLED\u3092\u6d88\u706f\r\n        RED_LED = OFF_LED;\r\n        Delay_10ms(10);\r\n        \/\/ param1\u3092-1\r\n        param1 --;\r\n    }\r\n    \/\/ \u77ed\u6642\u9593\u70b9\u706f\u30eb\u30fc\u30d7\r\n    while (param2 &gt; 0)\r\n    {\r\n        \/\/\u30e2\u30cb\u30bf\u30fcLED\u3092\u70b9\u706f\r\n        RED_LED = ON_LED;\r\n        Delay_10ms(20);\r\n        \/\/ \u30e2\u30cb\u30bf\u30fcLED\u3092\u6d88\u706f\r\n        RED_LED = OFF_LED;\r\n        Delay_10ms(10);\r\n        \/\/ param2\u3092-1\r\n        param2 --;\r\n    }\r\n    Delay_10ms(20);\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ 12F1822 Interrupt Routine\r\n\/\/ ------------------------------\r\n\/\/ I2C\u306e\u30de\u30b9\u30bf\u30fc\u3068\u30b9\u30ec\u30fc\u30d6\u3068\u306e\u3084\u308a\u53d6\u308a\u306f\u3001\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u306e\u8aac\u660e\u304c\u8a00\u8449\u8db3\u3089\u305a\u306a\u305f\u3081\u306b\r\n\/\/ \u975e\u5e38\u306b\u5224\u308a\u3065\u3089\u3044\u3002\u305f\u3060\u3057\u3001\u5224\u3063\u3066\u3057\u307e\u3046\u3068\u4f55\u3060\u305d\u308c\u3060\u3051\u304b\u3001\u3068\u306a\u308b\u3002\r\n\/\/\r\n\/\/ \u7279\u306b\u30b9\u30ec\u30fc\u30d6\u5074\u3067\u3042\u308c\u3053\u308c\u8a2d\u5b9a\u3057\u305f\u308a\u5224\u5b9a\u3084\u51e6\u7406\u306b\u5fc5\u8981\u306a\u306e\u306f\u6b21\u306e\u30d3\u30c3\u30c8\r\n\/\/ \u30fbD\/A\u20261=SSP1BUF\u306e\u4e2d\u306f\u30c7\u30fc\u30bf\u30010=SSP1BUF\u306e\u4e2d\u306f\u30a2\u30c9\u30ec\u30b9(\u7a7a\u3063\u307d\u2026\u7a7a\u306e\u8aad\u307f\u51fa\u3057\u8981\u6c42\u6642)\r\n\/\/ \u30fbR\/W\u20261=\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u53d7\u4fe1\u30010=\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u3078\u9001\u4fe1\r\n\/\/ \u30fbBF\u20261=\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u5165\u3063\u3066\u3044\u308b(\u7a7a\u306e\u8aad\u307f\u51fa\u3057\u8981\u6c42\u6642\u3082)\u30010=\u30d0\u30c3\u30d5\u30a1\u306f\u7a7a\u3063\u307d\r\n\/\/ \u30fbCKP\u2026\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\u3068\u304d\u3001\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u9001\u4fe1\u3059\u308b\u3068\u304d\u306b1\u306b\u3057\u3066SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3059\u308b\r\n\/\/ \u30fbSSP1IF\u2026\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u3001\u306a\u3093\u304b\u3057\u305f\u3089\u30af\u30ea\u30a2\u3059\u308b\r\n\/\/ \u30fbSEN\u2026\u30de\u30b9\u30bf\u30fc\u304b\u3089\u30c7\u30fc\u30bf\u3092\u53d7\u4fe1\u3059\u308b\u6642\u306b\u3001\u30bd\u30d5\u30c8\u5074\u3067CKP\u3092\u5236\u5fa1\u3059\u308b\u305f\u3081\u306b1\u306b\u3059\u308b\u30020\u3060\u3068\u3046\u307e\u304f\u52d5\u304b\u306a\u3044\u3088!!\r\n\/\/(\u30fbS\u2026\u30b9\u30bf\u30fc\u30c8\u30d3\u30c3\u30c8\u3001\u7279\u306b\u4f7f\u308f\u306a\u304f\u3066\u3082\u3044\u3044\u6c17\u304c\u3059\u308b)\r\n\/\/\r\n\/\/ \u3067\u3001\u5224\u5b9a\u306b\u4f7f\u3046\u30d3\u30c3\u30c8\u304c\u591a\u3044\u3051\u3069\u3001\u57fa\u672c\u7684\u306b\u306fSSP1STAT\u306a\u306e\u3067\u3001\u30de\u30b9\u30af\u3057\u3066\u4e00\u62ec\u5224\u5b9a\u3059\u308c\u3070OK\u3002\r\nstatic void interrupt int_func()\r\n{\r\n    char status_data;\r\n    char temp_buffer;\r\n\r\n    \/\/ \u5168\u5272\u308a\u8fbc\u307f\u3092\u7981\u6b62(=0) (Global Interrupt Enable bit ... INTCON)\r\n    GIE = 0;\r\n\r\n    \/\/ MSSP\u5272\u308a\u8fbc\u307f(=1)\u306a\u3089 (Synchronous Serial Port (MSSP) Interrupt Flag bit ... PIR1)\r\n    if (SSP1IF == 1)\r\n    {\r\n        \/\/ MSSP\u5272\u308a\u8fbc\u307f\u7981\u6b62(=0) (Synchronous Serial Port (MSSP) Interrupt Enable bit ... PIE1)\r\n        SSP1IE = 0;\r\n        \/\/ MSSP\u5272\u308a\u8fbc\u307f\u30af\u30ea\u30a2(=0) (Synchronous Serial Port (MSSP) Interrupt Flag bit ... PIR1)\r\n        SSP1IF = 0;\r\n\r\n        \/\/ SSP1STAT\u3092\u5224\u5b9a\u7528\u5909\u6570\u306b\u8a2d\u5b9a\u3002D\/A\u3001R\/W\u3001BF\u30d3\u30c3\u30c8\u3092\u30de\u30b9\u30af\r\n        status_data = SSP1STAT &amp; 0b00100101;\r\n\r\n        \/\/ \u30a2\u30c9\u30ec\u30b9(D\/A=0)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u3078\u9001\u4fe1(R\/W=0)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u3042\u308b(BF=1)\u306a\u3089\r\n        if (status_data == 0b00000001)\r\n        {\r\n            \/\/ SSP1BUF\u3092\u7a7a\u8aad\u307f\u3057\u3066\r\n            temp_buffer = SSP1BUF;\r\n            \/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092\u521d\u671f\u5316\r\n            rx_count = 0;\r\n            \/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n            CKP = 1;\r\n        }\r\n        \/\/ \u30c7\u30fc\u30bf(D\/A=1)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u3078\u9001\u4fe1(R\/W=0)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u3042\u308b(BF=1)\u306a\u3089\r\n        else if (status_data == 0b00100001)\r\n        {\r\n            \/\/ SSP1BUF\u304b\u3089\u30c7\u30fc\u30bf\u3092\u8aad\u307f\u51fa\u3057\u3066\u3001\u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u306e\u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u306b\u8a2d\u5b9a\r\n            rx_buffer&#x5B;rx_count] = SSP1BUF;\r\n\r\n            \/\/ \u53d7\u4fe1\u30c7\u30fc\u30bf\u304c0x00(\u30c7\u30ea\u30df\u30bf)\u306a\u3089\r\n            if (rx_buffer&#x5B;rx_count] == 0x00)\r\n            {\r\n                \/\/ --------------------------------------------------------------------------------\r\n                \/\/ (\u3068\u308a\u3042\u3048\u305a)\u30c7\u30fc\u30bf\u8981\u6c42\u306a\u3089 REQUEST MODULE DATA\r\n                \/\/ --------------------------------------------------------------------------------\r\n                if (rx_buffer&#x5B;1] == 0x11)\r\n                {\r\n                    \/\/ \u3068\u308a\u3042\u3048\u305abuffer\u306b\u30c0\u30df\u30fc\u30c7\u30fc\u30bf\u3092\u5165\u308c\u308b\u3002\r\n                    tx_buffer&#x5B;0] = 'A';\r\n                    tx_buffer&#x5B;1] = 'B';\r\n                    tx_buffer&#x5B;2] = 'C';\r\n                    tx_buffer&#x5B;3] = 'D';\r\n                    tx_buffer&#x5B;4] = 'E';\r\n                    tx_buffer&#x5B;5] = 'F';\r\n                    tx_buffer&#x5B;6] = 'G';\r\n                    tx_buffer&#x5B;7] = 'H';\r\n                    \/\/ \u5b9f\u969b\u306b\u9001\u4fe1\u3055\u308c\u308b\u306e\u306fA,B,C,D\u3060\u3051\u306e\u306f\u305a\r\n                }\r\n                \/\/ --------------------------------------------------------------------------------\r\n                \/\/ \u4e0a\u8a18\u4ee5\u5916\u306e\u5834\u5408\u306b\u306f\r\n                \/\/ --------------------------------------------------------------------------------\r\n                else\r\n                {\r\n                    \/\/ \u3068\u308a\u3042\u3048\u305a\u547d\u4ee4\u3055\u308c\u305f\u30b3\u30de\u30f3\u30c9\u3092\u305d\u306e\u307e\u307e\u8fd4\u3059\u3088\u3046\u306b\u3057\u3088\u3046\u3002:-P\r\n                    tx_buffer&#x5B;0] = rx_buffer&#x5B;1];\r\n                }\r\n                \/\/ --------------------------------------------------------------------------------\r\n                \/\/ \u5fc5\u8981\u306a\u3089\u30e1\u30c3\u30bb\u30fc\u30b8\u53d7\u4fe1\u3057\u305f\u3088\u30d5\u30e9\u30b0\u3067\u3082\u7acb\u3066\u3066\u30e1\u30a4\u30f3\u30eb\u30fc\u30d7\u5185\u3067\u51e6\u7406\u3057\u3066\u3082\u3089\u3046\r\n                \/\/ --------------------------------------------------------------------------------\r\n                \/\/ I2C\u53d7\u4fe1\u5b8c\u4e86\u30d5\u30e9\u30b0\u3092\u8a2d\u5b9a(=\u53d7\u4fe1\u5b8c\u4e86)\r\n                i2c_flag = 1;\r\n            }\r\n            \/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092+1\r\n            rx_count ++;\r\n            \/\/ \u53d7\u4fe1\u30c7\u30fc\u30bf\u304c\u30d0\u30c3\u30d5\u30a1\u3044\u3063\u3071\u3044\u306b\u306a\u3063\u305f\u308a\u3057\u305f\u3089\u30d5\u30e9\u30b0\u3067\u3082\u7acb\u3066\u3066\u30a8\u30e9\u30fc\u51e6\u7406\u3068\u304b\u3059\u308b\r\n            if (rx_count &gt;= RX_BUFF_SIZE)\r\n            {\r\n                rx_count = 0;\r\n            }\r\n            \/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n            CKP = 1;\r\n        }\r\n        \/\/ \u30a2\u30c9\u30ec\u30b9(D\/A=0)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u53d7\u4fe1(R\/W=1)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u3042\u308b(BF=1)\u306a\u3089\r\n        else if (status_data == 0b00000101)\r\n        {\r\n            \/\/ SSP1BUF\u3092\u7a7a\u8aad\u307f\u3057\u3066\r\n            temp_buffer = SSP1BUF;\r\n            \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092\u521d\u671f\u5316\r\n            tx_count = 0;\r\n            \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u306e\u6700\u521d\u306e\u30c7\u30fc\u30bf\u3092SSP1BUF\u306b\u8a2d\u5b9a\r\n            SSP1BUF = tx_buffer&#x5B;tx_count];\r\n            \/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n            CKP = 1;\r\n            \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092+1;\r\n            tx_count ++;\r\n        }\r\n        \/\/ \u30c7\u30fc\u30bf(D\/A=1)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u53d7\u4fe1(R\/W=1)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u304c\u7a7a(BF=0)\u306a\u3089\r\n        else if (status_data == 0b00100100)\r\n        {\r\n            \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u306e\u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u306e\u30c7\u30fc\u30bf\u3092SSP1BUF\u306b\u8a2d\u5b9a\r\n            SSP1BUF = tx_buffer&#x5B;tx_count];\r\n            \/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n            CKP = 1;\r\n            \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092+1;\r\n            tx_count ++;\r\n            \/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u304c\u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u3092\u8d8a\u3048\u305d\u3046\u306b\u306a\u3063\u305f\u308a\u3057\u305f\u3089\u30d5\u30e9\u30b0\u3067\u3082\u7acb\u3066\u3066\u30a8\u30e9\u30fc\u51e6\u7406\u3068\u304b\u3059\u308b\r\n            if (tx_count &gt;= TX_BUFF_SIZE)\r\n            {\r\n                tx_count = 0;\r\n            }\r\n        }\r\n        \/\/ \u3053\u308c\u3089\u4ee5\u5916\u306f\r\n        else\r\n        {\r\n            \/\/ SSP1BUF\u3092\u7a7a\u8aad\u307f\u3057\u3066\r\n            temp_buffer = SSP1BUF;\r\n            \/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u6b21\u306e\u547d\u4ee4\u3092\u4fc3\u3059\r\n            CKP = 1;\r\n        }\r\n        \/\/ MSSP\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Synchronous Serial Port (MSSP) Interrupt Enable bit ... PIE1)\r\n        SSP1IE = 1;\r\n    }\r\n    \/\/ \u5168\u5272\u308a\u8fbc\u307f\u3092\u8a31\u53ef(=1) (Global Interrupt Enable bit ... INTCON)\r\n    GIE = 1;\r\n}\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Setup\r\n\/\/ --------------------------------------------------\r\n\/\/ ------------------------------\r\n\/\/ Setup 12F1822\r\n\/\/ ------------------------------\r\nvoid setup(void)\r\n{\r\n    \/\/ OSCCON: OSCILLATOR CONTROL REGISTER PIC\u305d\u306e\u3082\u306e\u306e\u5185\u90e8\u30af\u30ed\u30c3\u30af\u3002OSCCON\u3092\u5909\u66f4\u3057\u305f\u3089_XTAL_FREQ\u3082\u5909\u66f4\u3059\u308b\u3053\u3068\r\n    \/\/ bit 7 SPLLEN: Software PLL Enable bit\r\n    \/\/     If PLLEN in Configuration Word 1 = 1:\r\n    \/\/         SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)\r\n    \/\/     If PLLEN in Configuration Word 1 = 0:\r\n    \/\/         1 = 4x PLL Is enabled\r\n    \/\/         0 = 4x PLL is disabled\r\n    \/\/ bit 6-3 IRCF: Internal Oscillator Frequency Select bits\r\n    \/\/     000x = 31 kHz LF\r\n    \/\/     0010 = 31.25 kHz MF\r\n    \/\/     0011 = 31.25 kHz HF(1)\r\n    \/\/     0100 = 62.5 kHz MF\r\n    \/\/     0101 = 125 kHz MF\r\n    \/\/     0110 = 250 kHz MF\r\n    \/\/     0111 = 500 kHz MF (default upon Reset)\r\n    \/\/     1000 = 125 kHz HF(1)\r\n    \/\/     1001 = 250 kHz HF(1)\r\n    \/\/     1010 = 500 kHz HF(1)\r\n    \/\/     1011 = 1MHz HF\r\n    \/\/     1100 = 2MHz HF\r\n    \/\/     1101 = 4MHz HF\r\n    \/\/     1110 = 8 MHz or 32 MHz HF(see Section 5.2.2.1 \u201cHFINTOSC\u201d)\r\n    \/\/     1111 = 16 MHz HF\r\n    \/\/ bit 2 Unimplemented: Read as \u20180\u2019\r\n    \/\/ bit 1-0 SCS: System Clock Select bits\r\n    \/\/     1x = Internal oscillator block\r\n    \/\/     01 = Timer1 oscillator\r\n    \/\/     00 = Clock determined by FOSC in Configuration Word 1\r\n    \/\/\r\n    \/\/ Note 1: Duplicate frequency derived from HFINTOSC.\r\n    OSCCON = 0b11101011;        \/\/ 4MHz\r\n\r\n    \/\/ ANSELA: PORTA ANALOG SELECT REGISTER \u30dd\u30fc\u30c8\u306eI\/O\u30e2\u30fc\u30c9\u306e\u8a2d\u5b9a\u3002\r\n    \/\/ bit7-5 : none (0)\r\n    \/\/ bit4   : ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively\r\n    \/\/            0 = Digital I\/O. Pin is assigned to port or digital special function.\r\n    \/\/            1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.\r\n    \/\/ bit3   : none (0)\r\n    \/\/ bit2   : ANSA2: Analog Select between Analog or Digital Function on pins RA2, respectively\r\n    \/\/ bit1   : ANSA1: Analog Select between Analog or Digital Function on pins RA1, respectively\r\n    \/\/ bit0   : ANSA0: Analog Select between Analog or Digital Function on pins RA0, respectively\r\n    ANSELA = 0b00000000;        \/\/ ALL digital\r\n\r\n    \/\/ OPTION_REG: OPTION REGISTER \u30aa\u30d7\u30b7\u30e7\u30f3\u8a2d\u5b9a\r\n    \/\/ bit7   : Weak Pull-up Enable bit 1 = All weak pull-ups are disabled, 0 = Weak pull-ups are enabled by individual WPUx latch values\r\n    \/\/ bit6   : Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2\/INT pin, 0 = Interrupt on falling edge of RA2\/INT pin\r\n    \/\/ bit5   : Timer0 Clock Source Select bit 1 = Transition on RA2\/T0CKI pin, 0 = Internal instruction cycle clock (FOSC\/4)\r\n    \/\/ bit4   : Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2\/T0CKI pin, 0 = Increment on low-to-high transition on RA2\/T0CKI pin\r\n    \/\/ bit3   : Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module, 0 = Prescaler is assigned to the Timer0 module\r\n    \/\/ bit2-0 : 000 = 1:2\r\n    \/\/        : 001 = 1:4\r\n    \/\/        : 010 = 1:8\r\n    \/\/        : 011 = 1:16\r\n    \/\/        : 100 = 1:32\r\n    \/\/        : 101 = 1:64\r\n    \/\/        : 110 = 1:128\r\n    \/\/        : 111 = 1:256\r\n    OPTION_REG = 0b00000000;    \/\/ \u7279\u306b\u306a\u3057\r\n\r\n    \/\/ WPUA: WEAK PULL-UP PORTA REGISTER \u30d7\u30eb\u30a2\u30c3\u30d7\u8a2d\u5b9a\r\n    \/\/ \u203b\u30a2\u30ca\u30ed\u30b0\u30ea\u30fc\u30c9\u3059\u308b\u3068\u304d\u306b\u306f\u30d7\u30eb\u30a2\u30c3\u30d7\u306f\u90aa\u9b54\u306a\u3060\u3051\u306a\u306e\u3067disabled\u306b\u3059\u308b\u3053\u3068\u3001\u30c7\u30d5\u30a9\u30eb\u30c8\u3067\u306fenabled\u306b\u306a\u3063\u3066\u3044\u305f H.A. 2012\/02\/23\r\n    \/\/ bit 7-6 Unimplemented: Read as \u20180\u2019\r\n    \/\/ bit 5-0 WPUB&lt;5:0&gt;: Weak Pull-up Register bits    \u2190\u8aa4\u690d\u304b\u306a\uff1f\r\n    \/\/     1 = Pull-up enabled\r\n    \/\/     0 = Pull-up disabled\r\n    \/\/\r\n    \/\/ Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.\r\n    \/\/      2: The weak pull-up device is automatically disabled if the pin is in configured as an output.\r\n    WPUA = 0b00000000;\r\n\r\n    \/\/ TRISA: PORTA TRI-STATE REGISTER \u30dd\u30fc\u30c8A\u8a2d\u5b9a\r\n    \/\/ bit7-6 : none (0)\r\n    \/\/ bit5   : TRISA5: PORTA Tri-State Control bits\r\n    \/\/            0 = PORTA pin configured as an output\r\n    \/\/            1 = PORTA pin configured as an input (tri-stated)\r\n    \/\/ bit4   : TRISA4: PORTA Tri-State Control bits\r\n    \/\/ bit3   : TRISA3: RA3 Port Tri-State Control bit. This bit is always \u20181\u2019 as RA3 is an input only\r\n    \/\/ bit2   : TRISA2: PORTA Tri-State Control bits\r\n    \/\/ bit1   : TRISA1: PORTA Tri-State Control bits\r\n    \/\/ bit0   : TRISA0: PORTA Tri-State Control bits\r\n    TRISA = 0b00000110;        \/\/ RA1,RA2\u3060\u3051I2C\u7528\u306binput\u30e2\u30fc\u30c9\r\n\r\n    \/\/ LATA: PORTA DATA LATCH REGISTER \u30dd\u30fc\u30c8A\u30e9\u30c3\u30c1\u30c7\u30fc\u30bf\u8a2d\u5b9a\r\n    \/\/ bit 7-6 Unimplemented: Read as \u20180\r\n    \/\/ bit 5-4 LATA: RA Output Latch Value bits(1)\r\n    \/\/ bit 3 Unimplemented: Read as \u20180\r\n    \/\/ bit 2-0 LATA: RA Output Latch Value bits(1)\r\n    \/\/\r\n    \/\/ Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return\r\n    \/\/ of actual I\/O pin values.\r\n    LATA = 0b00000000;        \/\/ \u7279\u306b\u306a\u3057\r\n\r\n    Delay_10ms(10);    \/\/ 100ms\u5f85\u3064\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ Setup MSSP\r\n\/\/ ------------------------------\r\nvoid setup_mssp(void)\r\n{\r\n    \/\/ MSSP1\u5236\u5fa1\u30c7\u30fc\u30bf\u8a2d\u5b9a\r\n    \/\/ bit 7 WCOL: Write Collision Detect bit\r\n    \/\/     Master mode:\r\n    \/\/         1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started\r\n    \/\/         0 = No collision\r\n    \/\/     Slave mode:\r\n    \/\/         1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software)\r\n    \/\/         0 = No collision\r\n    \/\/ bit 6 SSP1OV: Receive Overflow Indicator bit(1)\r\n    \/\/     In SPI mode:\r\n    \/\/         1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR\r\n    \/\/             is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting\r\n    \/\/             data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is\r\n    \/\/             initiated by writing to the SSP1BUF register (must be cleared in software).\r\n    \/\/         0 = No overflow\r\n    \/\/     In I2 C mode:\r\n    \/\/         1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a \u201cdon\u2019t care\u201d in Transmit\r\n    \/\/             mode (must be cleared in software).\r\n    \/\/         0 = No overflow\r\n    \/\/ bit 5 SSP1EN: Synchronous Serial Port Enable bit\r\n    \/\/     In both modes, when enabled, these pins must be properly configured as input or output\r\n    \/\/     In SPI mode:\r\n    \/\/         1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)\r\n    \/\/         0 = Disables serial port and configures these pins as I\/O port pins\r\n    \/\/     In I2 C mode:\r\n    \/\/         1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)\r\n    \/\/         0 = Disables serial port and configures these pins as I\/O port pins\r\n    \/\/ bit 4 CKP: Clock Polarity Select bit\r\n    \/\/     In SPI mode:\r\n    \/\/         1 = Idle state for clock is a high level\r\n    \/\/         0 = Idle state for clock is a low level\r\n    \/\/     In I2 C Slave mode:\r\n    \/\/         SCL release control\r\n    \/\/         1 = Enable clock\r\n    \/\/         0 = Holds clock low (clock stretch). (Used to ensure data setup time.)\r\n    \/\/     In I2 C Master mode:\r\n    \/\/         Unused in this mode\r\n    \/\/ bit 3-0 SSP1M: Synchronous Serial Port Mode Select bits\r\n    \/\/         0000 = SPI Master mode, clock = FOSC\/4\r\n    \/\/         0001 = SPI Master mode, clock = FOSC\/16\r\n    \/\/         0010 = SPI Master mode, clock = FOSC\/64\r\n    \/\/         0011 = SPI Master mode, clock = TMR2 output\/2\r\n    \/\/         0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled\r\n    \/\/         0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I\/O pin\r\n    \/\/         0110 = I2C Slave mode, 7-bit address\r\n    \/\/         0111 = I2C Slave mode, 10-bit address\r\n    \/\/         1000 = I2C Master mode, clock = FOSC \/ (4 * (SSP1ADD+1))(4)\r\n    \/\/         1001 = Reserved\r\n    \/\/         1010 = SPI Master mode, clock = FOSC\/(4 * (SSP1ADD+1))\r\n    \/\/         1011 = I2C firmware controlled Master mode (Slave idle)\r\n    \/\/         1100 = Reserved\r\n    \/\/         1101 = Reserved\r\n    \/\/         1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled\r\n    \/\/         1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled\r\n    \/\/\r\n    \/\/ Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register.\r\n    \/\/      2: When enabled, these pins must be properly configured as input or output.\r\n    \/\/      3: When enabled, the SDA and SCL pins must be configured as inputs.\r\n    \/\/      4: SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode.\r\n    SSP1CON1 = 0b00110110;    \/\/ SSP1EN = 1, CKP = 1, SSP1M = Slave mode 7bit\r\n\r\n    \/\/ bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)\r\n    \/\/     In Master mode:\r\n    \/\/         1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.\r\n    \/\/         0 = Start condition Idle\r\n    \/\/     In Slave mode:\r\n    \/\/         1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)\r\n    \/\/         0 = Clock stretching is disabled\r\n    \/\/\r\n    \/\/ Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be\r\n    \/\/ set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).\r\n    SEN = 1;    \/\/ Start Condition Enabled bit ... SSP1CON2) \u2190\u30de\u30b9\u30bf\u30fc\u304b\u3089\u30c7\u30fc\u30bf\u3092\u53d7\u3051\u53d6\u308b\u306a\u3089\u8a2d\u5b9a\u5fc5\u8981\r\n\r\n    \/\/ \u3053\u306e\u30c7\u30d0\u30a4\u30b9\u306eI2C\u30a2\u30c9\u30ec\u30b9\u3092\u8a2d\u5b9a\r\n    SSP1ADD = I2C_ADDR &lt;&lt; 1;\r\n\r\n    \/\/ MSSP1\u5272\u308a\u8fbc\u307f\u521d\u671f\u5316\r\n    \/\/ bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit\r\n    \/\/     1 = Interrupt is pending\r\n    \/\/     0 = Interrupt is not pending\r\n    SSP1IF = 0;\r\n\r\n    Delay_10ms(10);    \/\/ 100ms\u5f85\u3064\r\n}\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Main loop\r\n\/\/ --------------------------------------------------\r\nvoid main(void)\r\n{\r\n    \/\/ 12F1822 \u521d\u671f\u8a2d\u5b9a\r\n    setup();\r\n    \/\/ MSSP \u521d\u671f\u8a2d\u5b9a\r\n    setup_mssp();\r\n    \/\/ \u30e2\u30cb\u30bf\u30fcLED\u3092\u70b9\u706f\r\n    LED_Bright(3, 0);\r\n\r\n    \/\/ MSSP\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Synchronous Serial Port (MSSP) Interrupt Enable bit ... PIE1)\r\n    SSP1IE = 1;\r\n    \/\/ \u5468\u8fba\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Peripheral Interrupt Enable bit ... INTCON)\r\n    PEIE = 1;\r\n    \/\/ \u5168\u5272\u308a\u8fbc\u307f\u3092\u8a31\u53ef(=1) (Global Interrupt Enable bit ... INTCON)\r\n    GIE = 1;\r\n    \/\/ I2C\u540c\u671f\u8a31\u53ef(=1) (Synchronous Serial Port Enable bit ... SSP1CON1)\r\n    SSPEN = 1;\r\n\r\n    \/\/ \u30e1\u30a4\u30f3\u30eb\u30fc\u30d7\r\n    while(1)\r\n    {\r\n        \/\/ I2C\u53d7\u4fe1\u5b8c\u4e86\u30d5\u30e9\u30b0\u304c\u30bb\u30c3\u30c8\u3055\u308c\u308b\u307e\u3067\u30eb\u30fc\u30d7\r\n        while(i2c_flag == 0)\r\n        {\r\n            \/\/ \u30eb\u30fc\u30d7\u3057\u7d9a\u3051\u308b\r\n        }\r\n\r\n        \/\/ \u3053\u3053\u3067\u4f55\u3089\u304b\u306e\u51e6\u7406\u3092\u3059\u308b\u5834\u5408\u306b\u306f\u3001I2C\u3068\u304b\u306e\u5272\u308a\u8fbc\u307f\u306b\u3064\u3044\u3066\u6ce8\u610f\u3057\u3064\u3064\u3001\r\n        \/\/ \u3069\u3061\u3089\u304b\u3068\u8a00\u3046\u3068\u3001\u5272\u308a\u8fbc\u307f\u95a2\u6570\u5185\u3067\u51e6\u7406\u3059\u308b\u306b\u306f\u9577\u3044\u51e6\u7406\u3084\u3001\u547d\u4ee4\u3092\u53d7\u3051\u3066\r\n        \/\/ \u3084\u308a\u3063\u3071\u3067\u3059\u3080\u51e6\u7406\u3092\u8a18\u8ff0\u3059\u308b\u3053\u3068\u3002(\u4f8b\uff1a\u30b9\u30a4\u30c3\u30c1ON\u3068\u304b\u30ea\u30e2\u30b3\u30f3\u9001\u4fe1\u3068\u304b)\r\n        \/\/\r\n        \/\/ \u30bb\u30f3\u30b5\u30fc\u30c7\u30fc\u30bf\u3092\u8981\u6c42\u3055\u308c\u305f\u5834\u5408\u306b\u306f\u3001\u3067\u304d\u308b\u3060\u3051\u7c21\u6f54\u306b\u3001\u77ed\u3044\u51e6\u7406\u6642\u9593\u3067\u3059\u3080\r\n        \/\/ \u3088\u3046\u306b\u3057\u3066\u3001\u5272\u308a\u8fbc\u307f\u95a2\u6570\u5185\u306b\u3066\u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u306b\u8a2d\u5b9a\u3057\u3066\u3057\u307e\u3046\u3053\u3068\u3002\r\n\r\n        \/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092\u5148\u982d\u306b\u623b\u3059\r\n        rx_count = 0;\r\n        \/\/ I2C\u53d7\u4fe1\u5b8c\u4e86\u30d5\u30e9\u30b0\u3092\r\n        i2c_flag = 0;\r\n\r\n        \/\/ \u30e2\u30cb\u30bf\u30fcLED\u3092\u70b9\u706f\r\n        LED_Bright(0,1);\r\n    }\r\n}\r\n<\/pre>\n","protected":false},"excerpt":{"rendered":"<p>PIC(12F1822)\u3092\u5229\u7528\u3057\u3066\u3001GVC(Arduino)\u3068I2C\u3067\u30c7\u30fc\u30bf\u306e\u3084\u308a\u53d6\u308a\u3092\u3059\u308b\u30b5\u30f3\u30d7\u30eb\u30bd\u30fc\u30b9\u3067\u3059\u3002 \u73fe\u5728\u7b56\u5b9a\u4e2d\u306eGVC\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u3067\u3001I2C\u306e\u30de\u30b9\u30bf\u30fc\u3067\u3042\u308bArduino\u304b\u3089\u3001\u30b9\u30ec\u30fc\u30d6\u3067\u3042\u308bPIC\u306b\u5bfe\u3057\u3066\u30c7 &hellip; <a href=\"https:\/\/www.gvc-on.net\/?page_id=153\">\u7d9a\u304d\u3092\u8aad\u3080 <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":521,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-153","page","type-page","status-publish","hentry"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/153","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=153"}],"version-history":[{"count":6,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/153\/revisions"}],"predecessor-version":[{"id":525,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/153\/revisions\/525"}],"up":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/521"}],"wp:attachment":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=153"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}