{"id":630,"date":"2014-02-25T16:57:07","date_gmt":"2014-02-25T07:57:07","guid":{"rendered":"http:\/\/www.gvc-on.net\/?page_id=630"},"modified":"2014-02-25T16:57:07","modified_gmt":"2014-02-25T07:57:07","slug":"pic%e7%94%a8%e5%85%b1%e9%80%9a%e3%83%95%e3%82%a1%e3%82%a4%e3%83%abpic_init-c","status":"publish","type":"page","link":"https:\/\/www.gvc-on.net\/?page_id=630","title":{"rendered":"PIC\u7528\u5171\u901a\u30d5\u30a1\u30a4\u30eb(pic_init.c)"},"content":{"rendered":"<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\n\/\/ --------------------------------------------------\r\n\/\/ Global Versatile Controler http:\/\/www.gvc-on.net\/\r\n\/\/ --------------------------------------------------\r\n\/\/ --------------------------------------------------\r\n\/\/ Revision Memo (Y.M.D Editor\/Memo)\r\n\/\/ --------------------------------------------------\r\n\/\/ \r\n\/\/ 2013.05.08 T.Kabu\r\n\/\/ GVC Rev.2\u3068\u3057\u3066\u306e\u3082\u308d\u3082\u308d\u3092\u5b9a\u7fa9\r\n\/\/ \r\n\r\n\/\/---------------------------------------------------\r\n\/\/ Include Header\r\n\/\/---------------------------------------------------\r\n\/\/ ----------------------------------------\r\n\/\/ Standard Header\r\n\/\/ ----------------------------------------\r\n#include &lt;xc.h&gt;\r\n#include &lt;plib.h&gt;\r\n#include &lt;htc.h&gt;\r\n#include &lt;stdio.h&gt;\r\n#include &lt;stdlib.h&gt;\r\n#include &lt;string.h&gt;\r\n\r\n\/\/ ----------------------------------------\r\n\/\/ User Header\r\n\/\/ ----------------------------------------\r\n\/\/ PIC Parameter define and initialize\r\n#include &quot;pic_init.h&quot;\r\n\r\n\/\/ GVC Parameter define and initialize\r\n#include &quot;gvc_init.h&quot;\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Variable Param\r\n\/\/ --------------------------------------------------\r\nfloat\tvdd_volt = 5.00;\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Function prototype\r\n\/\/ --------------------------------------------------\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Sub Routine (pic_init.c)\r\n\/\/ --------------------------------------------------\r\n\/\/ ------------------------------\r\n\/\/ Delay 10m sec\r\n\/\/ ------------------------------\r\nvoid Delay_10ms(unsigned char time)\r\n{\r\n\t\/\/ _XTAL_FREQ\u3068\u3044\u3046\u5b9a\u6570\u3092\u5ba3\u8a00\u3059\u308b\u3053\u3068\u3002PIC\u305d\u306e\u3082\u306e\u306e\u5185\u90e8\u30af\u30ed\u30c3\u30afOSCCON\u3092\u5909\u66f4\u3057\u305f\u3089_XTAL_FREQ\u3082\u5909\u66f4\u3059\u308b\u3053\u3068\r\n\t\/\/ time\u30921\u6e1b\u3089\u3057\u3064\u306410ms\u5f85\u3064\u3002\u4f8b\uff1atime=100\u306a\u3089100x10ms=1000ms=1s\u5f85\u3064\r\n\twhile(time--)\r\n\t{\r\n\t\t\/\/ wait 10ms\r\n\t\t__delay_ms(10);\r\n\t}\r\n}\r\n\r\n\/\/ ----------------------------------------\r\n\/\/ Setup 18F26K22\r\n\/\/ ----------------------------------------\r\nvoid init_pic_18F26K22(void)\r\n{\r\n\t\/\/ ------------------------------\r\n\t\/\/ PIC\u306e\u52d5\u4f5c\u30af\u30ed\u30c3\u30af\u5b9a\u7fa9\u3002\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u3061\u306a\u307f\u306b\u52d5\u4f5c\u30af\u30ed\u30c3\u30af\u3092\u5909\u66f4\u3057\u305f\u3089_XTAL_FREQ\u3082\u5909\u66f4\u3059\u308b\u3053\u3068\r\n\t\/\/ bit7   : 0 = \u5b8c\u5168OFF\u30011 = SCS\u6b21\u7b2c\u3002(SLEEP\u547d\u4ee4\u6642)\r\n\t\/\/ bit6-4 : (\u4ee5\u4e0b\u306f\u5185\u90e8OSC\u4f7f\u7528\u6642)\r\n\t\/\/        : 111 = HFINTOSC    (16 MHz)\r\n\t\/\/        : 110 = HFINTOSC\/2  (8 MHz)\r\n\t\/\/        : 101 = HFINTOSC\/4  (4 MHz)\r\n\t\/\/        : 100 = HFINTOSC\/8  (2 MHz)\r\n\t\/\/        : 011 = HFINTOSC\/16 (1 MHz)\r\n\t\/\/ bit3   : OSC\u8d77\u52d5\u30bf\u30a4\u30e0\u30a2\u30a6\u30c8 \u30b9\u30c6\u30fc\u30bf\u30b9\r\n\t\/\/        : 1 = \u30c7\u30d0\u30a4\u30b9\u306fCONFIG1H\u30ec\u30b8\u30b9\u30bf\u306eFOSC&lt;3:0&gt;\u304c\u5b9a\u7fa9\u3059\u308b\u30af\u30ed\u30c3\u30af\u306b\u3088\u3063\u3066\u52d5\u4f5c\u4e2d\r\n\t\/\/        : 0 = \u30c7\u30d0\u30a4\u30b9\u306f\u5185\u90e8OSC(HFINTOSC, MFINTOSC or LFINTOSC)\u306b\u3088\u308a\u52d5\u4f5c\u4e2d\r\n\t\/\/ bit2   : HFINTOSC \u5468\u6ce2\u6570\u5b89\u5b9a\u72b6\u614b\u30d3\u30c3\u30c8\r\n\t\/\/        : 1 = HFINTOSC \u306e\u5468\u6ce2\u6570\u304c\u5b89\u5b9a\u3057\u3066\u3044\u308b\r\n\t\/\/        : 0 = HFINTOSC \u306e\u5468\u6ce2\u6570\u304c\u5b89\u5b9a\u3057\u3066\u3044\u306a\u3044\r\n\t\/\/ bit1-0 : 1x = Internal OSC\r\n\t\/\/        : 01 = Secondary (SOSC) oscillator\r\n\t\/\/        : 00 = Primary clock (determined by FOSC&lt;3:0&gt; in CONFIG1H)\r\n\tOSCCON  = 0b01110010; \t\t\/\/ \u30a2\u30a4\u30c9\u30eb\u30e2\u30fc\u30c9\u300116MHz(HFINTOSC)\u3001\u3001INTOSC\u4f7f\u7528\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8A\u306eI\/O\u30e2\u30fc\u30c9\u306e\u8a2d\u5b9a\u3002\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7-6 : Unimplemented: Read as \u20180\u2019\r\n\t\/\/ bit5   : ANSA5: RA5 Analog Select bit\r\n\t\/\/        : 1 = Digital input buffer disabled\r\n\t\/\/        : 0 = Digital input buffer enabled\r\n\t\/\/ bit4   : Unimplemented: Read as \u20180\u2019\r\n\t\/\/ bit3-0 : ANSA&lt;3:0&gt;: RA&lt;3:0&gt; Analog Select bit\r\n\t\/\/        : 1 = Digital input buffer disabled\r\n\t\/\/        : 0 = Digital input buffer enabled\r\n\tANSELA = 0b00000000;\t\t\/\/ ALL digital\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8B\u306eI\/O\u30e2\u30fc\u30c9\u306e\u8a2d\u5b9a\u3002\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7-6 : Unimplemented: Read as \u20180\u2019\r\n\t\/\/ bit5-0 : ANSB&lt;5:0&gt; RB&lt;5:0&gt; Analog Select bit\r\n\t\/\/        : 1 = Digital input buffer disabled\r\n\t\/\/        : 0 = Digital input buffer enabled\r\n\tANSELB = 0b00000000;\t\t\/\/ ALL digital\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8C\u306eI\/O\u30e2\u30fc\u30c9\u306e\u8a2d\u5b9a\u3002\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7-2 : ANSC&lt;5:0&gt; RC&lt;5:0&gt; Analog Select bit\r\n\t\/\/        : 1 = Digital input buffer disabled\r\n\t\/\/        : 0 = Digital input buffer enabled\r\n\t\/\/ bit1-0 : Unimplemented: Read as \u20180\u2019\r\n\tANSELC = 0b00000000;\t\t\/\/ ALL digital\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8A\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RA7 1 = input, 0 = output\r\n\t\/\/ bit6   : RA6 1 = input, 0 = output\r\n\t\/\/ bit5   : RA5 1 = input, 0 = output\r\n\t\/\/ bit4   : RA4 1 = input, 0 = output\r\n\t\/\/ bit3   : RA3 1 = input, 0 = output\r\n\t\/\/ bit2   : RA2 1 = input, 0 = output\r\n\t\/\/ bit1   : RA1 1 = input, 0 = output\r\n\t\/\/ bit0   : RA0 1 = input, 0 = output\r\n\tTRISA = 0b00000000;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8B\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RB7 1 = input, 0 = output\r\n\t\/\/ bit6   : RB6 1 = input, 0 = output\r\n\t\/\/ bit5   : RB5 1 = input, 0 = output\r\n\t\/\/ bit4   : RB4 1 = input, 0 = output\r\n\t\/\/ bit3   : RB3 1 = input, 0 = output\r\n\t\/\/ bit2   : RB2 1 = input, 0 = output\r\n\t\/\/ bit1   : RB1 1 = input, 0 = output\r\n\t\/\/ bit0   : RB0 1 = input, 0 = output\r\n\tTRISB = 0b00000000;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8C\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RC7 1 = input, 0 = output\r\n\t\/\/ bit6   : RC6 1 = input, 0 = output\r\n\t\/\/ bit5   : RC5 1 = input, 0 = output\r\n\t\/\/ bit4   : RC4 1 = input, 0 = output\r\n\t\/\/ bit3   : RC3 1 = input, 0 = output\r\n\t\/\/ bit2   : RC2 1 = input, 0 = output\r\n\t\/\/ bit1   : RC1 1 = input, 0 = output\r\n\t\/\/ bit0   : RC0 1 = input, 0 = output\r\n\tTRISC = 0b10011001;\t\t\t\/\/ RC7\u3092\u30b7\u30ea\u30a2\u30ebRX\u7528\u306b\u3001RC4,RC3\u3092I2C\u7528\u306b\u3001RC0\u3092\u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u7528\u306binput\u30e2\u30fc\u30c9\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8A\u30e9\u30c3\u30c1\u30c7\u30fc\u30bf\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RA7 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit6   : RA6 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit5   : RA5 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit4   : RA4 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit3   : RA3 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit2   : RA2 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit1   : RA1 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit0   : RA0 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\tLATA = 0b00000000;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8B\u30e9\u30c3\u30c1\u30c7\u30fc\u30bf\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RB7 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit6   : RB6 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit5   : RB5 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit4   : RB4 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit3   : RB3 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit2   : RB2 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit1   : RB1 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit0   : RB0 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\tLATB = 0b00000000;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8C\u30e9\u30c3\u30c1\u30c7\u30fc\u30bf\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RC7 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit6   : RC6 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit5   : RC5 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit4   : RC4 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit3   : RC3 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit2   : RC2 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit1   : RC1 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\t\/\/ bit0   : RC0 \u30dd\u30fc\u30c8I\/O \u51fa\u529b\u30e9\u30c3\u30c1\u30ec\u30b8\u30b9\u30bf \u30d3\u30c3\u30c8\r\n\tLATC = 0b00000000;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc0\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit 7   : TMR0ON: Timer0 On\/Off Control bit\r\n\t\/\/     1 = Enables Timer0\r\n\t\/\/     0 = Stops Timer0\r\n\t\/\/ bit 6   : T08BIT: Timer0 8-bit\/16-bit Control bit\r\n\t\/\/     1 = Timer0 is configured as an 8-bit timer\/counter\r\n\t\/\/     0 = Timer0 is configured as a 16-bit timer\/counter\r\n\t\/\/ bit 5   : T0CS: Timer0 Clock Source Select bit\r\n\t\/\/     1 = Transition on T0CKI pin\r\n\t\/\/     0 = Internal instruction cycle clock (CLKOUT) \u30bf\u30a4\u30de\u30fc\u3068\u3057\u3066\u4f7f\u3046\u306a\u30890\u306b\u3059\u308b\u3053\u3068\r\n\t\/\/ bit 4   : T0SE: Timer0 Source Edge Select bit\r\n\t\/\/     1 = Increment on high-to-low transition on T0CKI pin\r\n\t\/\/     0 = Increment on low-to-high transition on T0CKI pin\r\n\t\/\/ bit 3   : PSA: Timer0 Prescaler Assignment bit\r\n\t\/\/     1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.\r\n\t\/\/     0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.\r\n\t\/\/ bit 2-0 : T0PS&lt;2:0&gt;: Timer0 Prescaler Select bits\r\n\t\/\/     111 = 1:256 prescale value\r\n\t\/\/     110 = 1:128 prescale value\r\n\t\/\/     101 = 1:64 prescale value\r\n\t\/\/     100 = 1:32 prescale value\r\n\t\/\/     011 = 1:16 prescale value\r\n\t\/\/     010 = 1:8 prescale value\r\n\t\/\/     001 = 1:4 prescale value\r\n\t\/\/     000 = 1:2 prescale value\r\n\tT0CON = 0b00000010;\t\t\t\/\/ Stops Timer0, 16bit, Internal, NONE, Prescaler assign, 1:8\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit 7-6 : TMRxCS&lt;1:0&gt;: Timer1\/3\/5 Clock Source Select bits\r\n\t\/\/     11 =Reserved. Do not use.\r\n\t\/\/     10 =Timer1\/3\/5 clock source is pin or oscillator:\r\n\t\/\/         If TxSOSCEN = 0:\r\n\t\/\/             External clock from TxCKI pin (on the rising edge)\r\n\t\/\/         If TxSOSCEN = 1:\r\n\t\/\/             Crystal oscillator on SOSCI\/SOSCO pins\r\n\t\/\/     01 =Timer1\/3\/5 clock source is system clock (FOSC)\r\n\t\/\/     00 =Timer1\/3\/5 clock source is instruction clock (FOSC\/4)\r\n\t\/\/ bit 5-4 : TxCKPS&lt;1:0&gt;: Timer1\/3\/5 Input Clock Prescale Select bits\r\n\t\/\/     11 = 1:8 Prescale value\r\n\t\/\/     10 = 1:4 Prescale value\r\n\t\/\/     01 = 1:2 Prescale value\r\n\t\/\/     00 = 1:1 Prescale value\r\n\t\/\/ bit 3   : TxSOSCEN: Secondary Oscillator Enable Control bit\r\n\t\/\/     1 = Dedicated Secondary oscillator circuit enabled\r\n\t\/\/     0 = Dedicated Secondary oscillator circuit disabled\r\n\t\/\/ bit 2   : TxSYNC: Timer1\/3\/5 External Clock Input Synchronization Control bit\r\n\t\/\/     TMRxCS&lt;1:0&gt; = 1X\r\n\t\/\/         1 = Do not synchronize external clock input\r\n\t\/\/         0 = Synchronize external clock input with system clock (FOSC)\r\n\t\/\/     TMRxCS&lt;1:0&gt; = 0X\r\n\t\/\/         This bit is ignored. Timer1\/3\/5 uses the internal clock when TMRxCS&lt;1:0&gt; = 1X.\r\n\t\/\/ bit 1   : TxRD16: 16-Bit Read\/Write Mode Enable bit\r\n\t\/\/     1 = Enables register read\/write of Timer1\/3\/5 in one 16-bit operation\r\n\t\/\/     0 = Enables register read\/write of Timer1\/3\/5 in two 8-bit operation\r\n\t\/\/ bit 0   : TMRxON: Timer1\/3\/5 On bit\r\n\t\/\/     1 = Enables Timer1\/3\/5\r\n\t\/\/     0 = Stops Timer1\/3\/5\r\n\t\/\/     Clears Timer1\/3\/5 Gate flip-flop\r\n\tT1CON = 0b00110010;\t\t\t\/\/ FOSC\/4, 1:8, disabled, ignored, 16bit, Timer1 Stop\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30b2\u30fc\u30c8\u5236\u5fa1\u30ec\u30b8\u30b9\u30bf\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit 7 TMRxGE: Timer1 Gate Enable bit\r\n\t\/\/     If TMRxON = 0:\r\n\t\/\/         This bit is ignored\r\n\t\/\/     If TMRxON = 1:\r\n\t\/\/         1 = Timer1 counting is controlled by the Timer1 gate function\r\n\t\/\/         0 = Timer1 counts regardless of Timer1 gate function\r\n\t\/\/ bit 6 T1GPOL: Timer1 Gate Polarity bit\r\n\t\/\/     1 = Timer1 gate is active-high (Timer1 counts when gate is high)\r\n\t\/\/     0 = Timer1 gate is active-low (Timer1 counts when gate is low)\r\n\t\/\/ bit 5 T1GTM: Timer1 Gate Toggle Mode bit\r\n\t\/\/     1 = Timer1 Gate Toggle mode is enabled\r\n\t\/\/     0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared\r\n\t\/\/     Timer1 gate flip-flop toggles on every rising edge.\r\n\t\/\/ bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit\r\n\t\/\/     1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate\r\n\t\/\/     0 = Timer1 gate Single-Pulse mode is disabled\r\n\t\/\/ bit 3 T1GGO\/DONE: Timer1 Gate Single-Pulse Acquisition Status bit\r\n\t\/\/     1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge\r\n\t\/\/     0 = Timer1 gate single-pulse acquisition has completed or has not been started\r\n\t\/\/     This bit is automatically cleared when T1GSPM is cleared.\r\n\t\/\/ bit 2 T1GVAL: Timer1 Gate Current State bit\r\n\t\/\/     Indicates the current state of the Timer1 gate that could be provided to TMRxH:TMRxL.\r\n\t\/\/     Unaffected by Timer1 Gate Enable (TMRxGE).\r\n\t\/\/ bit 1-0 T1GSS&lt;1:0&gt;: Timer1 Gate Source Select bits\r\n\t\/\/     00 = Timer1 Gate pin\r\n\t\/\/     01 = Timer0 overflow output\r\n\t\/\/     10 = Comparator 1 optionally synchronized output (SYNCC1OUT)\r\n\t\/\/     11 = Comparator 2 optionally synchronized output (SYNCC2OUT)(1)\r\n\tT1GCON = 0b00000000;\t\t\/\/ ignored, active-low, disabled, disabled ...\r\n\t\r\n\tDelay_10ms(10);\t\/\/ 100ms\u5f85\u3064\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ Setup EUSART 18F26K22\r\n\/\/ ------------------------------\r\nvoid init_eusart_18F26K22(void)\r\n{\r\n\t\/\/ EUSART\u6a5f\u80fd\u306e\u8a2d\u5b9a\u3092\u884c\u3046\r\n\t\/\/ ANSELC\u306e\u8a2d\u5b9a\u306b\u6ce8\u610f\u3001\u521d\u671f\u8a2d\u5b9a\u306fALL Digital\u306b\u306a\u3063\u3066\u3044\u308b\u304b\u3089\u3044\u3044\u3051\u3069\r\n\tTXSTA1 = 0b00100100;\t\t\/\/ \u9001\u4fe1\u8a2d\u5b9a TXEN=1, SYNC=0, BRGH(\u9ad8\u901f\u30dc\u30fc\u30ec\u30fc\u30c8)=1\r\n\tRCSTA1 = 0b10010000;\t\t\/\/ \u53d7\u4fe1\u8a2d\u5b9a SPEN=1, CREN=1\r\n\tSPBRG1 = 103;\t\t\t\t\/\/ 9600bps\u306b\u8a2d\u5b9a\u3001FOSC\u306e\u5909\u66f4\u306b\u3088\u308a\u5024\u304c\u5909\u308f\u308b\u306e\u3067\u6ce8\u610f\r\n}\r\n\r\n\/\/ ----------------------------------------\r\n\/\/ Get temperature port voltage\r\n\/\/ ----------------------------------------\r\nint get_port_voltage(char port_num)\r\n{\r\n\tint  voltage = 0;\/\/ \u6e29\u5ea6\u30c7\u30fc\u30bf\u3001\u4e0a\u4f4d8\u30d3\u30c3\u30c8\u306bint\u306elow\u304c\u3001\u4e0b\u4f4d8\u30d3\u30c3\u30c8\u306bint\u306ehi\u304c\u5165\u308b\r\n\t\r\n\t\/\/ FVR\u304c\u5b89\u5b9a\u3059\u308b\u307e\u3067\u5f85\u3064\r\n\twhile ( 1 )\r\n\t{\r\n\t\t\/\/ FVR\u304c\u5b89\u5b9a\u3057\u305f\u306a\u3089\r\n\t\tif (VREFCON0bits.FVRST == 1)\r\n\t\t{\r\n\t\t\t\/\/ \u30eb\u30fc\u30d7\u3092\u629c\u3051\u308b\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\t\/\/ FVR\u304c\u5b89\u5b9a\u3057\u3066\u3044\u306a\u3044\u306a\u3089\r\n\t\telse\r\n\t\t{\r\n\t\t\t\/\/ \u4f55\u3082\u3057\u306a\u3044\r\n\t\t}\r\n\t}\r\n\t\r\n\t\/\/ AD\u5909\u63db\u5236\u5fa1\u30ec\u30b8\u30b9\u30bf0\u8a2d\u5b9a A\/D CONTROL REGISTER 0\r\n\t\/\/ bit 7 Unimplemented: Read as \u20180\u2019\r\n\t\/\/ bit 6-2 CHS&lt;4:0&gt;: Analog Channel Select bits\r\n\t\/\/     00000 = AN0\r\n\t\/\/     00001 = AN1\r\n\t\/\/     00010 = AN2\r\n\t\/\/     00011 = AN3\r\n\t\/\/     00100 = AN4\r\n\t\/\/     01000 = AN8\r\n\t\/\/     01001 = AN9\r\n\t\/\/     01010 = AN10\r\n\t\/\/     01011 = AN11\r\n\t\/\/     01100 = AN12\r\n\t\/\/     01101 = AN13\r\n\t\/\/     01110 = AN14\r\n\t\/\/     01111 = AN15\r\n\t\/\/     10000 = AN16\r\n\t\/\/     10001 = AN17\r\n\t\/\/     10010 = AN18\r\n\t\/\/     10011 = AN19\r\n\t\/\/     11100 = Reserved\r\n\t\/\/     11101 = CTMU\r\n\t\/\/     11110 = DAC\r\n\t\/\/     11111 = FVR BUF2 (1.024V\/2.048V\/2.096V Volt Fixed Voltage Reference)(2)\r\n\t\/\/ bit 1 GO\/DONE: A\/D Conversion Status bit\r\n\t\/\/     1 = A\/D conversion cycle in progress. Setting this bit starts an A\/D conversion cycle.\r\n\t\/\/         This bit is automatically cleared by hardware when the A\/D conversion has completed.\r\n\t\/\/     0 = A\/D conversion completed\/not in progress\r\n\t\/\/ bit 0 ADON: ADC Enable bit\r\n\t\/\/     1 = ADC is enabled\r\n\t\/\/     0 = ADC is disabled and consumes no operating current\r\n\/\/\tADCON0 = 0b00001000;\t\/\/ AN2 \u3067AD\u5909\u63db\u6709\u52b9\u306b\u8a2d\u5b9a\r\n\tADCON0 = (port_num &lt;&lt; 2);\r\n\t\r\n\t\/\/ \u521d\u671f\u8a2d\u5b9a(ADCON0,ADCON1)\u306e\u8a2d\u5b9a\u304c\u7d42\u308f\u3063\u3066\u304b\u3089\u3001AD\u5909\u63db\u3092\u6709\u52b9\u306b\u3059\u308b\r\n\tADCON0bits.ADON = 1;\r\n\t\/\/ \u96fb\u5727\u6e2c\u5b9a\u306e\u305f\u3081\u300110us\u79d2\u5f85\u3061\r\n\t__delay_us(10);    \/\/ wait 10us\r\n\t\r\n\t\/\/ \u521d\u671f\u8a2d\u5b9a(ADCON0,ADCON1)\u306e\u8a2d\u5b9a\u304c\u7d42\u308f\u3063\u3066\u304b\u3089\u3001AD\u5909\u63db\u3092\u6709\u52b9\u306b\u3059\u308b\r\n\tADCON0bits.GODONE = 1;\r\n\t\r\n\t\/\/ ADGO\u304c1\u306e\u9593\u306f\u5f85\u3061\r\n\twhile(ADCON0bits.GODONE)\r\n\t{\r\n\t\t\/\/ \u96fb\u5727\u6e2c\u5b9a\u306e\u305f\u3081\u300110us\u79d2\u5f85\u3061\r\n\t\t__delay_us(10);    \/\/ wait 10us\r\n\t};\r\n\t\/\/ \u96fb\u5727\u30c7\u30fc\u30bf\u3092\u8aad\u307f\u51fa\u3057\u3066\u6e29\u5ea6\u30c7\u30fc\u30bf\u306b\u8a2d\u5b9a\r\n\tvoltage = ADRESH &lt;&lt; 8;\r\n\tvoltage += ADRESL;\r\n\t\r\n\t\/\/ \u6e29\u5ea6\u30c7\u30fc\u30bf\u3092\u8fd4\u3059\r\n\treturn voltage;\r\n}\r\n\r\n\/\/ ----------------------------------------\r\n\/\/ Get Vdd Voltage\r\n\/\/ ----------------------------------------\r\nfloat get_vdd(void)\r\n{\r\n\t\/\/ float \u3092\u30b9\u30bf\u30c3\u30af\u306b\u3044\u3063\u3071\u3044\u7528\u610f\u3057\u3088\u3046\u3068\u3059\u308b\u3068\u3001\u30aa\u30fc\u30d0\u30fc\u30d5\u30ed\u30fc\u306b\u306a\u308b\u3088!! &quot;fixup overflow referencing psect...&quot; \u3068\u3044\u308f\u308c\u3066\r\n\t\/\/ \u30ea\u30f3\u30af\u3067\u304d\u306a\u304b\u3063\u305f\u3089\u3001\u5909\u6570\u306fstatic\u5ba3\u8a00\u3067\u3061\u3083\u3093\u3068\u56fa\u5b9a\u30e1\u30e2\u30ea\u9818\u57df\u3092\u4f7f\u304a\u3046 2013.06.10 T.Kabu\r\n\r\n\tint\t\tan_data = 0;\r\n\tfloat\tan_volt = 0;\r\n\t\r\n\t\/\/ PIC\u306e\u30dd\u30fc\u30c8(AN3)\u304b\u3089\u73fe\u5728\u306e\u96fb\u5727\u30c7\u30fc\u30bf\u3092\u53d6\u5f97\u3059\u308b\r\n\tan_data = get_port_voltage(3);\r\n\t\r\n\t\/\/ \u96fb\u5727\u30c7\u30fc\u30bf\u3092\u96fb\u5727\u306b\u5909\u63db(\u62b5\u6297\u30671\/2\u306b\u5206\u5727\u3057\u3066\u3044\u308b\u306e\u3067\u4e8c\u500d\u3059\u308b\u306e\u3092\u5fd8\u308c\u305a\u306b)\r\n\tan_volt = (FVR_VOLT \/ 1024) * an_data * 2;\r\n\t\r\n\treturn an_volt;\r\n}\r\n<\/pre>\n","protected":false},"excerpt":{"rendered":"<p>\/\/ &#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8211; \/\/ Global Versatile Controler http:\/\/www.gvc-on.net\/ \/\/  &hellip; <a href=\"https:\/\/www.gvc-on.net\/?page_id=630\">\u7d9a\u304d\u3092\u8aad\u3080 <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":622,"menu_order":11,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-630","page","type-page","status-publish","hentry"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/630","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=630"}],"version-history":[{"count":1,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/630\/revisions"}],"predecessor-version":[{"id":631,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/630\/revisions\/631"}],"up":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/622"}],"wp:attachment":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=630"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}