{"id":644,"date":"2014-02-25T17:16:58","date_gmt":"2014-02-25T08:16:58","guid":{"rendered":"http:\/\/www.gvc-on.net\/?page_id=644"},"modified":"2014-02-25T17:22:24","modified_gmt":"2014-02-25T08:22:24","slug":"%e8%b5%a4%e5%a4%96%e7%b7%9a%e3%83%aa%e3%83%a2%e3%82%b3%e3%83%b3%e3%83%a2%e3%82%b8%e3%83%a5%e3%83%bc%e3%83%ab%e7%94%a8%e3%83%97%e3%83%ad%e3%82%b0%e3%83%a9%e3%83%a0slave_ir_txrx_18f26k22-c","status":"publish","type":"page","link":"https:\/\/www.gvc-on.net\/?page_id=644","title":{"rendered":"\u8d64\u5916\u7dda\u30ea\u30e2\u30b3\u30f3\u30e2\u30b8\u30e5\u30fc\u30eb\u7528\u30d7\u30ed\u30b0\u30e9\u30e0(slave_ir_txrx_18f26k22.c)"},"content":{"rendered":"
\r\n\/\/ --------------------------------------------------\r\n\/\/ Global Versatile Controler http:\/\/www.gvc-on.net\/\r\n\/\/ --------------------------------------------------\r\n\/\/ --------------------------------------------------\r\n\/\/ Revision Memo (Y.M.D Editor\/Memo)\r\n\/\/ --------------------------------------------------\r\n\/\/\r\n\/\/ \u8d64\u5916\u7dda\u30e2\u30b8\u30e5\u30fc\u30eb\u7528\r\n\/\/\r\n\/\/ \u8d64\u5916\u7dda\u30e2\u30b8\u30e5\u30fc\u30eb\u306f\u5927\u304d\u304f\u5225\u3051\u3066\u4ee5\u4e0b\u306e\u4e8c\u3064\u306e\u52d5\u4f5c\u3092\u884c\u3046\r\n\/\/ \u30fb\u65e2\u5b58\u8d64\u5916\u7dda\u30ea\u30e2\u30b3\u30f3\u4fe1\u53f7\u306e\u53d7\u4fe1(\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0)\r\n\/\/ \u30fb\u6307\u5b9a\u3055\u308c\u305f\u8d64\u5916\u7dda\u30ea\u30e2\u30b3\u30f3\u4fe1\u53f7\u306e\u9001\u4fe1\r\n\/\/ \u3082\u3068\u3082\u3068\u306e\u8d64\u5916\u7dda\u4fe1\u53f7\u3092\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u3057\u3066\u305d\u308c\u3092\u5143\u306bPWM\u3092\u518d\u751f\u3059\u308b\u3068\u3044\u3046\u304a\u30d0\u30ab\u5b66\u7fd2\u30ea\u30e2\u30b3\u30f3\u307f\u305f\u3044\u306a\u611f\u3058\r\n\/\/ \r\n\/\/ \u30e1\u30e2\u30ea\u306e\u95a2\u4fc2\u3067GVC\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u306b\u305d\u3063\u305f\u5f62\u3067\u30e1\u30e2\u30ea\u5171\u6709\u3059\u308b\r\n\/\/ \r\n\/\/ ------------------------------\r\n\/\/ BASE\r\n\/\/ ------------------------------\r\n\/\/ 2013.07.10 T.Kabu \u6e2c\u8ddd\u304b\u3089\u8d64\u5916\u7dda\u306b\u6d41\u7528\r\n\/\/ 2013.09.06 T.Kabu \u9001\u4fe1\u6642\u306b\u6319\u52d5\u4e0d\u5be9\u306b\u306a\u308b\u306e\u306f\u3001\u8d64\u5916\u7ddaLED\u3067\u30c9\u30ab\u30f3!!\u3068\u9001\u4fe1\u3057\u3088\u3046\u3068\u3057\u305f\u3068\u304d\u306e\u96fb\u6e90\u30e9\u30a4\u30f3\u306e\u96fb\u5727\u964d\u4e0b\u304c\u539f\u56e0\u3089\u3057\u3044\r\n\/\/                   \u4e00\u3064\u306f\u3001\u30c7\u30ab\u30c3\u30d7\u30ea\u30f3\u30b0\u30b3\u30f3\u30c7\u30f3\u30b5(\u30d0\u30a4\u30d1\u30b9\u30b3\u30f3\u30c7\u30f3\u30b5)\u3068\u3057\u3066100uF\u306eMLCC\u3068\u304b\u96fb\u89e3\u30b3\u30f3\u30c7\u30f3\u30b5\u3092\u3064\u3051\u308b\u3053\u3068\r\n\/\/                   \u3067\u96fb\u5727\u964d\u4e0b\u3092\u304b\u306a\u308a\u9632\u3052\u308b\u304c\u3001\u8d64\u5916\u7ddaLED\u3068\u76f4\u5217\u306b\u63a5\u7d9a\u3057\u3066\u3044\u308bR\u30925\u03a9\u7a0b\u5ea6\u306b\u3057\u3066\u3055\u3089\u306b\u5927\u96fb\u6d41\u3092\u6d41\u305d\u3046\u3068\u3059\u308b\r\n\/\/                   \u3068\u3001\u96fb\u5727\u964d\u4e0b\u304c\u767a\u751f\uff1f\u3057\u3066PIC\u304c\u30ea\u30bb\u30c3\u30c8\u3059\u308b\u3002\u3053\u306e\u539f\u56e0\u3092\u63a2\u308b\u305f\u3081\u306e\u4ed5\u8fbc\u307f\u3092\u57cb\u3081\u8fbc\u3080\u3002\r\n\/\/ 2013.11.03 T.Kabu \u30a8\u30a2\u30b3\u30f3\u306e\u30ea\u30e2\u30b3\u30f3\u4fe1\u53f7\u3068GVC\u7a7a\u306e\u518d\u9001\u4fe1\u53f7\u3092\u307f\u3066\u307f\u308b\u3068\u3001\u3069\u3046\u3082GVC\u304b\u3089\u306e\u65b9\u304c\u9593\u5ef6\u3073\u3057\u3066\u3044\u3066\u3001\u9577\u3044\u5834\u54085ms\u304f\u3089\u3044\u305a\u308c\u308b(3%\u304f\u3089\u3044)\r\n\/\/                   \u30b7\u30d3\u30a2\u306a\u5224\u5b9a\u3092\u3057\u3066\u3044\u308b\u5834\u5408\u306b\u306f\u3001\u3053\u308c\u3060\u3068NG\u306b\u306a\u308b\u306e\u304b\u3082\u3057\u308c\u306a\u3044\u306e\u3067\u3001\u3082\u3046\u5c11\u3057\u304d\u3063\u3061\u308a\u3057\u3066\u307f\u308b\r\n\/\/                   \u30fb\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u309250us\u3067\u306a\u304f52us\u3068\u3059\u308b\r\n\/\/                   \u30fb\u9001\u4fe1\u6642\u306eON\/OFF\u6642\u9593\u3092\u77ed\u304f\u3059\u308b\r\n\/\/ 2013.11.21 T.Kabu \u53d7\u4fe1\u6642\u306e\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u3092\u5272\u308a\u8fbc\u307f\u3067\u3084\u308b\u306e\u306f\u3088\u3044\u306e\u3060\u304c\u3001\u9001\u4fe1\u6642\u306e\u30d0\u30a4\u30c8\u3092\u307e\u305f\u3050(char\u306e\u914d\u5217\u306a\u308a\u30dd\u30a4\u30f3\u30bf\u306a\u308a\u3067\u6b21\u306b\u884c\u304f)\u3060\u3051\u3067\r\n\/\/                   34us\u3068\u304b\u639b\u304b\u3063\u3061\u3083\u3046\u306e\u3067\u3001\u305d\u3053\u306738KHz\u306e\u30ad\u30e3\u30ea\u30a2\u304c\u6b62\u307e\u308b\u4e8b\u306b\u306a\u3063\u3066\u3057\u307e\u3046\u3002(1\/38kHz\uff1d26.3us)\r\n\/\/                   \u3053\u308c\u3060\u3068\u304d\u308c\u3044\u3067\u306f\u306a\u3044\u306e\u3067\u3001\u9001\u4fe1\u3082\u5272\u308a\u8fbc\u307f\u51e6\u7406\u306738kHz\u3092\u9001\u4fe1\u3057\u3064\u3064ON\/OFF\u3059\u308b\u4e8b\u306b\u3059\u308b\u3002\r\n\/\/                   \u3068\u3044\u3046\u3053\u3068\u3067\u9001\u4fe1\u306b\u306fTimer3\u3092\u3064\u304b\u3063\u3066\u30d7\u30ea\u30b9\u30b1\u30fc\u30e9\u30921:8\u304b\u30891:4\u306b\u3057\u3066\u9001\u4fe1\u3059\u308b\r\n\/\/ 2013.11.26 T.Kabu \u9001\u4fe1\u306e\u4ed5\u65b9\u3092\u3001PWM\u306738KHz\u3092\u4f5c\u308a\u3064\u3064\u3001\u3053\u308c\u3092STR1A\u3067ON\/OFF\u3059\u308b\u3053\u3068\u3067\u30ad\u30e3\u30ea\u30a2\u306eON\/OFF\u3068\u3059\u308b\u3088\u3046\u306b\u3057\u3066\u307f\u308b\r\n\/\/ 2013.11.28 T.Kabu \u8d64\u5916\u7ddaLED\u3092\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u3068\u306f1\/0\u53cd\u8ee2\u3055\u305b\u305f\u72b6\u614b\u3067\u70b9\u706f\u3059\u308b\u3068\u3001\u3070\u3063\u3061\u308a!!\r\n\/\/                   \u2026\u306a\u306e\u3067\u3001\u3053\u308c\u3067GVC\u306e\u30b5\u30f3\u30d7\u30eb\u30e2\u30b8\u30e5\u30fc\u30eb\u306f\u4e00\u901a\u308a\u958b\u767a\u3067\u304d\u305f\u306e\u3067\u3001\u6574\u7406\u6574\u9813\u3001\u6e05\u66f8\u3057\u3066\u30ea\u30ea\u30fc\u30b9\u306b\u5411\u3051\u3066\u524d\u9032\u3042\u308b\u306e\u307f!!\r\n\/\/ 2013.12.03 T.Kabu \u3055\u3089\u306b\u30c1\u30e5\u30fc\u30cb\u30f3\u30b0\u3057\u3066\u3001\u53d7\u4fe1\/\u9001\u4fe1\u6642\u306b\u305d\u308c\u305e\u308c\u4e8b\u524d\u306e\u30a6\u30a7\u30a4\u30c8\u3068\u304b\u30011\u30d5\u30ec\u30fc\u30e0\u306e\u7d42\u308f\u308a\u306e\u691c\u51fa\u3068\u304b\u3092\u3057\u3063\u304b\u308a\u3057\u3066\u307f\u305f\r\n\r\n\/\/---------------------------------------------------\r\n\/\/ Include Header\r\n\/\/---------------------------------------------------\r\n\/\/ ----------------------------------------\r\n\/\/ Standard Header\r\n\/\/ ----------------------------------------\r\n#include <xc.h>\r\n#include <plib.h>\r\n#include <htc.h>\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n\r\n\/\/ ----------------------------------------\r\n\/\/ User Header\r\n\/\/ ----------------------------------------\r\n\/\/ Pragma Header\r\n#include "pragma.h"\r\n\r\n\/\/ PIC Parameter define and initialize\r\n#include "pic_init.h"\r\n\r\n\/\/ GVC Parameter define and initialize\r\n#include "gvc_init.h"\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Const Define\r\n\/\/ --------------------------------------------------\r\n#define VERSION "=== GVC SLAVE MODULE DEVICE PROGRAM for 18F26K22 (IR) ==="\r\n\r\n\/\/ PIC\u306eI2C\u30a2\u30c9\u30ec\u30b9\u3001\u9069\u6642\u5909\u66f4\u3059\u308b\u3053\u3068\r\n#define\tI2C_ADDR\t\t\t0x10\t\t\t\t\t\/\/ \u30e2\u30b8\u30e5\u30fc\u30eb\u3054\u3068\u306b\u30a2\u30c9\u30ec\u30b9\u3092\u5909\u3048\u308b\u3053\u3068!!\r\n\r\n\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u30b5\u30a4\u30ba\r\n#define SERIAL_RCV_BUFFSIZE\t16\r\n#define SERIAL_RCV_BUFFRING\t15\t\t\t\t\t\t\/\/ SERIAL_RCV_BUFFSIZE\u304b\u30891\u6e1b\u3089\u3057\u305f\u5024\u3092\u8a2d\u5b9a\r\n\r\n\/\/ \u30b7\u30ea\u30a2\u30eb\u30d0\u30c3\u30d5\u30a1\u30b5\u30a4\u30ba\r\n\/\/\/#define SERIAL_BUFF_SIZE\t3096\t\t\t\t\t\/\/ \u4f7f\u308f\u306a\u3044\r\n\r\n\/\/ I2C\u30d0\u30c3\u30d5\u30a1\u30b5\u30a4\u30ba\r\n\/\/\/#define RX_BUFF_SIZE\t\t3096\t\t\t\t\t\/\/ \u4f7f\u308f\u306a\u3044\r\n\/\/\/#define TX_BUFF_SIZE\t\t3096\t\t\t\t\t\/\/ \u4f7f\u308f\u306a\u3044\r\n\r\n#define MAIN_BUFF_SIZE\t\t3096\t\t\t\t\t\/\/ \u3053\u306e\u8d64\u5916\u7dda\u30e2\u30b8\u30e5\u30fc\u30eb\u306e\u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u30b5\u30a4\u30ba\r\n#define SUB_BUFF_SIZE\t\t256\t\t\t\t\t\t\/\/ \u3053\u306e\u8d64\u5916\u7dda\u30e2\u30b8\u30e5\u30fc\u30eb\u306e\u30b5\u30d6\u30d0\u30c3\u30d5\u30a1\u30b5\u30a4\u30ba\r\n\r\n#define IR_BUFF_SIZE\t\t3000\t\t\t\t\t\/\/ MAIN_BUFF_SIZE\u304b\u3089GVC\u306e\u30d8\u30c3\u30c0\u60c5\u5831\u5206\u3060\u3051\u5f15\u3044\u305f\u5024\u306b\u3059\u308b\u3053\u3068\u2605\r\n\r\n\/\/ \u30b7\u30ea\u30a2\u30eb\u30d0\u30c3\u30d5\u30a1\u3068I2C\u30d0\u30c3\u30d5\u30a1\u306f\u3001\u305d\u308c\u305e\u308c\u306eGVC\u30e2\u30b8\u30e5\u30fc\u30eb\u3067\u60f3\u5b9a\u3057\u3066\u3044\u308b\u30c7\u30fc\u30bf\u306b\u5408\u308f\u305b\u305f\u30b5\u30a4\u30ba\u306b\u3059\u308b\u3053\u3068\r\n\/\/ \u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u3060\u3051\u306f\u3001\u3069\u3046\u304c\u3093\u3070\u3063\u3066\u30823096\u30d0\u30a4\u30c8\u3092\u3072\u3068\u3064\u78ba\u4fdd\u3057\u305f\u3089\u7d42\u308f\u308a\u306a\u306e\u3067\u3001\u305d\u308c\u305e\u308c\u3067\u4f7f\u3044\u56de\u3057\u3092\u3057\u306a\u3044\u3068\u3044\u3051\u306a\u3044\u306e\u3067\u3001\u4f7f\u3044\u65b9\u306b\u6ce8\u610f\u3059\u308b\u3053\u3068\r\n\r\n#define IR_TX_MAX\t\t\t1\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u3092\u518d\u9001\u4fe1\u3059\u308b\u56de\u6570\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Variable Param\r\n\/\/ --------------------------------------------------\r\n\/\/ \u5272\u308a\u8fbc\u307f\u51e6\u7406\u5185\u3067\u306e\u30ec\u30b8\u30b9\u30bf\u306e\u5024\u3092\u683c\u7d0d\u3059\u308b\u5909\u6570\u306f\u3053\u3053\u3067\u5ba3\u8a00\u3059\u308b\u3053\u3068\u3001\u5272\u308a\u8fbc\u307f\u51e6\u7406\u5185\u3067\u5ba3\u8a00\u3057\u3066\u306f\u3044\u3051\u306a\u3044!! T.Kabu 2013.05.14\r\nunsigned char reg_RCSTA1;\t\t\t\t\t\t\t\/\/ \u53d7\u4fe1\u30b9\u30c6\u30fc\u30bf\u30b9\u30ec\u30b8\u30b9\u30bf\r\nunsigned char reg_SSP1STAT;\t\t\t\t\t\t\t\/\/ SSP1\u30b9\u30c6\u30fc\u30bf\u30b9\u30ec\u30b8\u30b9\u30bf\r\nunsigned char temp_buffer;\t\t\t\t\t\t\t\/\/ SSP1BUF\u306e\u7a7a\u8aad\u307f\u7528\r\nGVC_I2C_MESSAGE_t * gvc_i2c_message;\t\t\t\t\/\/ GVC I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u7528\u30dd\u30a4\u30f3\u30bf(tx_buffer\/rx_buffer\u306b\u304b\u3076\u305b\u308b)\r\n\r\nunsigned char serial_rcvptr;\t\t\t\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf\r\nunsigned char serial_readptr\t;\t\t\t\t\t\/\/ \u53d7\u4fe1\u8aad\u307f\u51fa\u3057\u30dd\u30a4\u30f3\u30bf\r\nunsigned char serial_rcvbuff[SERIAL_RCV_BUFFSIZE];\t\/\/ \u53d7\u4fe1\u30ea\u30f3\u30b0\u30d0\u30c3\u30d5\u30a1(RCREG1)\r\n\r\n\/\/\/unsigned char serial_buffer[SUB_BUFF_SIZE];\t\t\t\/\/ \u30b7\u30ea\u30a2\u30eb\u30d0\u30c3\u30d5\u30a1(\u4f5c\u696d\u7528)\u3000\u2192\u3000sub_buffer\u306b\u3059\u308b\r\n\r\n\/\/\/unsigned char rx_buffer[RX_BUFF_SIZE];\t\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u3000\u2192\u3000\u3068\u308a\u3042\u3048\u305amain_buffer\u306b\u3059\u308b\r\nunsigned int  rx_count = 0;\t\t\t\t\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\r\n\r\n\/\/\/unsigned char tx_buffer[TX_BUFF_SIZE];\t\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u3000\u2192\u3000\u3068\u308a\u3042\u3048\u305asub_buffer\u306b\u3059\u308b\u3001\u3067\u3082\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u306b\u306fmain_buffer\u3067\u306a\u3044\u3068\r\nunsigned int  tx_count = 0;\t\t\t\t\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\r\n\r\nunsigned int  i2c_data_len;\t\t\t\t\t\t\t\/\/ I2C\u306e\u30c7\u30fc\u30bf\u9577(data_len)\r\n\r\nstatic char   i2c_status = 0;\t\t\t\t\t\t\/\/ I2C\u30b9\u30c6\u30fc\u30bf\u30b9 0:\u5f85\u6a5f\u72b6\u614b 1:\u30c7\u30fc\u30bf\u53d7\u4fe1\u4e2d 10:\u30c7\u30fc\u30bf\u53d7\u4fe1\u5b8c\u4e86\r\n\r\nunsigned char ir_mode = 0;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30b8\u30e5\u30fc\u30eb\u52d5\u4f5c\u30e2\u30fc\u30c9(0=\u53d7\u4fe1\u30c7\u30fc\u30bf\u304c\u3042\u308c\u3070\u518d\u9001\u4fe1\u30011=\u8aad\u307f\u53d6\u308a)\r\nunsigned char ir_rxmax = 0;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u6700\u5927\u53d7\u4fe1\u30e2\u30fc\u30c9(0=\u901a\u5e38\u30011=\u6700\u5927)\r\n\r\nunsigned char main_buffer[MAIN_BUFF_SIZE];\t\t\t\/\/ \u8d64\u5916\u7dda\u30e2\u30b8\u30e5\u30fc\u30eb\u5171\u901a\u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\r\nunsigned char sub_buffer[SUB_BUFF_SIZE];\t\t\t\/\/ \u8d64\u5916\u7dda\u30e2\u30b8\u30e5\u30fc\u30eb\u5171\u901a\u30b5\u30d6\u30d0\u30c3\u30d5\u30a1\r\n\r\n\/\/unsigned char ir_buffer[IR_BUFF_SIZE];\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d0\u30c3\u30d5\u30a1\r\nunsigned char * ir_buffer;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf(\u5b9f\u30a8\u30ea\u30a2\u3067\u306a\u304f\u3066main_buffer\u3092GVC\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u306b\u5909\u63db\u3057\u305fdata[]\u90e8\u5206\u306b\u306a\u308b)\r\nunsigned char ir_saved_buffer[8];\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u5f85\u907f\u30d0\u30c3\u30d5\u30a1(\u4ed6\u306e\u30b3\u30de\u30f3\u30c9\u3067\u5148\u982d\u306e\u6570\u30d0\u30a4\u30c8\u304c\u7834\u58ca\u3055\u308c\u308b\u304b\u3089)\r\nunsigned char ir_data;\t\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\r\nunsigned char ir_status;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u3072\u3068\u3064\u524d\u306e\u72b6\u614b\r\nunsigned int  ir_count;\t\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\r\nunsigned char ir_bit;\t\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\r\nunsigned char ir_trx_flag;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0(0=none, 1=\u53d7\u4fe1\u4e2d, 2=\u9001\u4fe1\u4e2d)\r\nunsigned char ir_rx_status;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b(0=none, 1=RXwait,2=RXing etc...)\r\nunsigned int  ir_same_count;\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf\r\nunsigned int  ir_data_len;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9577\r\n\r\nunsigned int  timer0_count;\t\t\t\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc0\u30ab\u30a6\u30f3\u30bf\r\nunsigned int  timer1_count;\t\t\t\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30ab\u30a6\u30f3\u30bf\r\nunsigned char timer0_h;\t\t\t\t\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc0\u306eHigh\u306e\u5024\r\nunsigned char timer0_l;\t\t\t\t\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc0\u306eLow\u306e\u5024\r\nunsigned char timer1_h;\t\t\t\t\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc1\u306eHigh\u306e\u5024\r\nunsigned char timer1_l;\t\t\t\t\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc1\u306eLow\u306e\u5024\r\n\r\nunsigned char ir_tx_count;\t\t\t\t\t\t\t\/\/ \u8d64\u5916\u7dda\u9001\u4fe1\u56de\u6570\r\nunsigned char ir_tx_data;\t\t\t\t\t\t\t\/\/ \u8d64\u5916\u7dda\u9001\u4fe1\u30d0\u30a4\u30c8\r\nunsigned char * ir_buffer_end;\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf\u306e\u6700\u5f8c\r\n\r\nconst char bit_mask_array[8] = {\t\t\t\t\t\/\/ \u30d3\u30c3\u30c8\u8a08\u7b97\u7528\u306e\u914d\u5217(AND\u3068\u304b\u3067\u3059\u3080\u3088\u3046\u306b)\r\n\t\t0b00000001,\r\n\t\t0b00000010,\r\n\t\t0b00000100,\r\n\t\t0b00001000,\r\n\t\t0b00010000,\r\n\t\t0b00100000,\r\n\t\t0b01000000,\r\n\t\t0b10000000\r\n};\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Function prototype\r\n\/\/ --------------------------------------------------\r\n\/\/ --------------------------------------------------\r\n\/\/ Sub Routine\r\n\/\/ --------------------------------------------------\r\n\/\/ ------------------------------\r\n\/\/ Recieve serialdata\r\n\/\/ ------------------------------\r\nchar rcv_serialdata(void)\r\n{\r\n\tunsigned char data;\r\n\t\r\n\t\/\/ \u8fd4\u308a\u5024\u7528\u30c7\u30fc\u30bf\u306b\u53d7\u4fe1\u30c7\u30fc\u30bf\u30b3\u30d4\u30fc\r\n\tdata = serial_rcvbuff[serial_readptr];\r\n\t\/\/ \u53d7\u4fe1\u8aad\u307f\u51fa\u3057\u30dd\u30a4\u30f3\u30bf\u3092\u52a0\u7b97\r\n\tserial_readptr ++;\r\n\t\/\/ \u53d7\u4fe1\u8aad\u307f\u51fa\u3057\u30dd\u30a4\u30f3\u30bf\u3092\u30ea\u30f3\u30b0\u308b\r\n\tserial_readptr &= SERIAL_RCV_BUFFRING;\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u30c7\u30fc\u30bf\u3092\u8fd4\u3059\r\n\treturn data;\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ Send IR RX DATA\r\n\/\/ ------------------------------\r\nvoid send_ir_rxdata(void)\r\n{\r\n\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf\u306e\u7d42\u4e86\u30dd\u30a4\u30f3\u30bf\u3092\u8a08\u7b97(10\u30d0\u30a4\u30c8\u306a\u3089 a+10\r\n\tir_buffer_end = ir_buffer + ir_data_len;\r\n\t\r\n\t\/\/ \u9001\u4fe1\u30eb\u30fc\u30d7\r\n\tdo\r\n\t{\r\n\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30dd\u30a4\u30f3\u30bf\u306e\u4e2d\u8eab\u3092\u9001\u4fe1\u3059\u308b\r\n\t\tsend_hexdata(*ir_buffer);\r\n\t\t\r\n\/*** START ***\r\n\t\t\/\/ ------------------------------\r\n\t\t\/\/ \u30d3\u30c3\u30c8\u5358\u4f4d\u3067\u9001\u4fe1\u3059\u308b\u5834\u5408\u306b\u306f\u3053\u3093\u306a\u611f\u3058\u3067\r\n\t\t\/\/ ------------------------------\r\n\t\t\/\/ \u5404\u30d3\u30c3\u30c8\u3054\u3068\u306b0\/1\u3092\u9001\u4fe1\u3059\u308b\u30eb\u30fc\u30d7\r\n\t\tfor (ir_bit = 0; ir_bit < 8; ir_bit++)\r\n\t\t{\r\n\t\t\twhile(TX1IF == 0);\t\/\/ \u9001\u4fe1\u53ef\u80fd\u306b\u306a\u308b\u307e\u3067\u5f85\u3064\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u8a72\u5f53\u30d3\u30c3\u30c8\u304c0\u306a\u3089\r\n\t\t\tif ( (*ir_buffer & bit_mask_array[ir_bit]) == 0 )\r\n\t\t\t{\r\n\t\t\t\t\/\/ Hi(=0)\u306e\u3068\u304d\r\n\t\t\t\tTXREG1 = 0x30;\r\n\t\t\t}\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u8a72\u5f53\u30d3\u30c3\u30c8\u304c1\u306a\u3089\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t\/\/ Low(=1)\u306e\u3068\u304d\r\n\t\t\t\tTXREG1 = 0x31;\r\n\t\t\t}\r\n\t\t}\r\n*** END ***\/\r\n\t\t\r\n\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30dd\u30a4\u30f3\u30bf\u3092\u52a0\u7b97\r\n\t\tir_buffer ++;\r\n\t\t\r\n\t} while (ir_buffer < ir_buffer_end);\t\/\/ \u7d42\u4e86\u30dd\u30a4\u30f3\u30bf\u307e\u3067\u9054\u3057\u3066\u3044\u306a\u3044\u306a\u3089\u9001\u4fe1\u30eb\u30fc\u30d7\r\n\t\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u3053\u306e\u30eb\u30fc\u30c1\u30f3\u3092\u629c\u3051\u308b\u3068ir_buffer\u30dd\u30a4\u30f3\u30bf\u306f\u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u6700\u5f8c\u306e\u6b21\u306b\u3059\u3063\u98db\u3093\u3067\u3044\u308b\u306e\u3067\u518d\u8a2d\u5b9a\u5fd8\u308c\u305a\u306b\r\n}\r\n\r\n\/\/ ----------------------------------------\r\n\/\/ Setup 18F26K22 for Analog Voltage\r\n\/\/ ----------------------------------------\r\nvoid init_pic_for_analogvoltage(void)\r\n{\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30dd\u30fc\u30c8A\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit7   : RA7 1 = input, 0 = output\r\n\t\/\/ bit6   : RA6 1 = input, 0 = output\r\n\t\/\/ bit5   : RA5 1 = input, 0 = output\r\n\t\/\/ bit4   : RA4 1 = input, 0 = output\r\n\t\/\/ bit3   : RA3 1 = input, 0 = output\r\n\t\/\/ bit2   : RA2 1 = input, 0 = output\r\n\t\/\/ bit1   : RA1 1 = input, 0 = output\r\n\t\/\/ bit0   : RA0 1 = input, 0 = output\r\n\tTRISA = 0b00001111;\t\t\/\/ RA0-RA3\u3092\u3092\u96fb\u5727\u6e2c\u5b9a\u7528\u306binput\u30e2\u30fc\u30c9\r\n\t\r\n\t\/\/ ANSELA: PORTA ANALOG SELECT REGISTER \u30dd\u30fc\u30c8\u306eI\/O\u30e2\u30fc\u30c9\u306e\u8a2d\u5b9a\u3002\r\n\t\/\/ bit7-6 : none (0)\r\n\t\/\/ bit5   : ANSA4: Analog Select between Analog or Digital Function on pins RA5, respectively\r\n\t\/\/            0 = Digital I\/O. Pin is assigned to port or digital special function.\r\n\t\/\/            1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.\r\n\t\/\/ bit4   : none (0)\r\n\t\/\/ bit3   : ANSA3: Analog Select between Analog or Digital Function on pins RA3, respectively\r\n\t\/\/ bit2   : ANSA2: Analog Select between Analog or Digital Function on pins RA2, respectively\r\n\t\/\/ bit1   : ANSA1: Analog Select between Analog or Digital Function on pins RA1, respectively\r\n\t\/\/ bit0   : ANSA0: Analog Select between Analog or Digital Function on pins RA0, respectively\r\n\tANSELA = 0b00001111;\t\/\/ AN0(=RA0),AN1(=RA1),AN2(=RA2),AN3(=RA3) Analog input\r\n\t\r\n\t\/\/ ADCON0 \u306f\u3001\u5b9f\u969b\u306b\u96fb\u5727\u3092\u8aad\u3080\u3068\u304d\u306b\u3001\u305d\u306e\u30dd\u30fc\u30c8\u3092\u6307\u5b9a\u3057\u306a\u3044\u3068\u3044\u3051\u306a\u3044\u306e\u3067\u3053\u3053\u3067\u306f\u3044\u3058\u3089\u306a\u3044\r\n\t\r\n\t\/\/ bit 7 TRIGSEL: Special Trigger Select bit\r\n\t\/\/     1 = Selects the special trigger from CTMU\r\n\t\/\/     0 = Selects the special trigger from CCP5\r\n\t\/\/ bit 6-4 Unimplemented: Read as \u20180\u2019\r\n\t\/\/ bit 3-2 PVCFG<1:0>: Positive Voltage Reference Configuration bits\r\n\t\/\/     00 = A\/D VREF+ connected to internal signal, AVDD\r\n\t\/\/     01 = A\/D VREF+ connected to external pin, VREF+\r\n\t\/\/     10 = A\/D VREF+ connected to internal signal, FVR BUF2\r\n\t\/\/     11 = Reserved (by default, A\/D VREF+ connected to internal signal, AVDD)\r\n\t\/\/ bit 1-0 NVCFG0<1:0>: Negative Voltage Reference Configuration bits\r\n\t\/\/     00 = A\/D VREF- connected to internal signal, AVSS\r\n\t\/\/     01 = A\/D VREF- connected to external pin, VREF-\r\n\t\/\/     10 = Reserved (by default, A\/D VREF+ connected to internal signal, AVSS)\r\n\t\/\/     11 = Reserved (by default, A\/D VREF+ connected to internal signal, AVSS)\r\n\/\/\/\tADCON1 = 0b00000000;\t\t\/\/ VREF+\u3001VREF-\u3068\u3082\u306b\u5185\u90e8\u4f9b\u7d66\u96fb\u5727Vdd\u306b\u5bfe\u3057\u3066\u306e\u5024\u3068\u306a\u308b\r\n\tADCON1 = 0b00001000;\t\t\/\/ VREF+\u306fFVR\u304b\u3089\u3001VREF-\u306fGND\u306b\u5bfe\u3057\u3066\u306e\u5024\u3068\u306a\u308b\r\n\t\r\n\t\/\/ AD\u5909\u63db\u5236\u5fa1\u30ec\u30b8\u30b9\u30bf2\u8a2d\u5b9a A\/D CONTROL REGISTER 2\r\n\t\/\/ bit 7 ADFM: A\/D Conversion Result Format Select bit\r\n\t\/\/     1 = Right justified\r\n\t\/\/     0 = Left justified\r\n\t\/\/ bit 6 Unimplemented: Read as \u20180\u2019\r\n\t\/\/ bit 5-3 ACQT<2:0>: A\/D Acquisition time select bits. Acquisition time is the duration that the A\/D charge holding\r\n\t\/\/         capacitor remains connected to A\/D channel from the instant the GO\/DONE bit is set until conversions\r\n\t\/\/         begins.\r\n\t\/\/     000 = 0(1)\r\n\t\/\/     001 = 2 TAD\r\n\t\/\/     010 = 4 TAD\r\n\t\/\/     011 = 6 TAD\r\n\t\/\/     100 = 8 TAD\r\n\t\/\/     101 = 12 TAD\r\n\t\/\/     110 = 16 TAD\r\n\t\/\/     111 = 20 TAD\r\n\t\/\/ bit 2-0 ADCS<2:0>: A\/D Conversion Clock Select bits\r\n\t\/\/     000 = FOSC\/2\r\n\t\/\/     001 = FOSC\/8\r\n\t\/\/     010 = FOSC\/32\r\n\t\/\/     011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)\r\n\t\/\/     100 = FOSC\/4\r\n\t\/\/     101 = FOSC\/16\r\n\t\/\/     110 = FOSC\/64\r\n\t\/\/     111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)\r\n\tADCON2 = 0b10110101;\t\/\/ \u53f3\u5bc4\u305b\u300116TAD\u3001FOSC\/16\r\n\t\r\n\t\/\/ \u96fb\u5727\u30ea\u30d5\u30a1\u30ec\u30f3\u30b9\u5236\u5fa1\u30ec\u30b8\u30b9\u30bf0 FIXED VOLTAGE REFERENCE CONTROL REGISTER\r\n\t\/\/ bit 7 FVREN: Fixed Voltage Reference Enable bit\r\n\t\/\/     0 = Fixed Voltage Reference is disabled\r\n\t\/\/     1 = Fixed Voltage Reference is enabled\r\n\t\/\/ bit 6 FVRST: Fixed Voltage Reference Ready Flag bit\r\n\t\/\/     0 = Fixed Voltage Reference output is not ready or not enabled\r\n\t\/\/     1 = Fixed Voltage Reference output is ready for use\r\n\t\/\/ bit 5-4 FVRS<1:0>: Fixed Voltage Reference Selection bits\r\n\t\/\/     00 = Fixed Voltage Reference Peripheral output is off\r\n\t\/\/     01 = Fixed Voltage Reference Peripheral output is 1x (1.024V)\r\n\t\/\/     10 = Fixed Voltage Reference Peripheral output is 2x (2.048V)(1)\r\n\t\/\/     11 = Fixed Voltage Reference Peripheral output is 4x (4.096V)(1)\r\n\t\/\/ bit 3-2 Reserved: Read as \u20180\u2019. Maintain these bits clear.\r\n\t\/\/ bit 1-0 Unimplemented: Read as \u20180\u2019.\r\n\tVREFCON0 = 0b10110000;\t\/\/ FVR\u6709\u52b9\u3001x4\u306e4.096V\u3068\u3059\u308b\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ Setup MSSP1 18F26K22\r\n\/\/ ------------------------------\r\nvoid init_mssp1_18F26K22(void)\r\n{\r\n\t\/\/ ------------------------------\r\n\t\/\/ MSSP1\u5236\u5fa1\u30c7\u30fc\u30bf\u8a2d\u5b9a \u30b9\u30ec\u30fc\u30d6\u3068\u3057\u3066\u8a2d\u5b9a\u3059\u308b\u5834\u5408\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit 7   : SMP 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)\r\n\t\/\/         :     0 = Slew rate control enabled for high speed mode (400 kHz)\r\n\t\/\/ bit 6   : CKE 1 = Enable input logic so that thresholds are compliant with SMbus specification\r\n\t\/\/         :     0 = Disable SMbus specific inputs\r\n\t\/\/ bit 5   : D\/A: Data\/Address bit (I2C mode only)\r\n\t\/\/         :     1 = Indicates that the last byte received or transmitted was data\r\n\t\/\/         :     0 = Indicates that the last byte received or transmitted was address\r\n\t\/\/ bit 4   : P: Stop bit\r\n\t\/\/         : (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)\r\n\t\/\/         :     1 = Indicates that a Stop bit has been detected last (this bit is \u20180\u2019 on Reset)\r\n\t\/\/         :     0 = Stop bit was not detected last\r\n\t\/\/ bit 3   : S: Start bit\r\n\t\/\/         : (I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)\r\n\t\/\/         :     1 = Indicates that a Start bit has been detected last (this bit is \u20180\u2019 on Reset)\r\n\t\/\/         :     0 = Start bit was not detected last\r\n\t\/\/ bit 2   : R\/W: Read\/Write bit information (I2C mode only)\r\n\t\/\/         : In I2 C Master mode:\r\n\t\/\/         :     1 = Transmit is in progress\r\n\t\/\/         :     0 = Transmit is not in progress\r\n\t\/\/         : OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.\r\n\t\/\/         : (\u3053\u306e\u30d3\u30c3\u30c8\u3068\u3001SEN\u3001RSEN\u3001PEN\u3001RCEN\u3001\u307e\u305f\u306fACKEN \u3068\u306e\u8ad6\u7406\u548c\u3092\u53d6\u308b\u3068\u3001\u30de\u30b9\u30bf\u30e2\u30fc\u30c9\u304c\u30a2\u30af\u30c6\u30a3\u30d6\u304b\u3069\u3046\u304b\u3092\u5224\u65ad\u3067\u304d\u308b)\r\n\t\/\/ bit 1   : UA: Update Address bit (10-bit I2C mode only)\r\n\t\/\/ bit 0   : BF: Buffer Full Status bit\r\n\t\/\/         : Receive (SPI and I2 C modes):\r\n\t\/\/         :     1 = Receive complete, SSPxBUF is full\r\n\t\/\/         :     0 = Receive not complete, SSPxBUF is empty\r\n\t\/\/         : Transmit (I2 C mode only):\r\n\t\/\/         :     1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full\r\n\t\/\/         :     0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty\r\n\tSSP1STAT = 0b00000000;\t\/\/ 400kHz Slew rate\r\n\t\r\n\t\/\/ bit7   : WCOL master(1 = Collision, 0 = No Collision), slave(1 = must be cleard, 0 = No Collision)\r\n\t\/\/ bit6   : SSP1OV SPI(pass), I2C(1 = overflow, 0 = not Overflow)\r\n\t\/\/ bit5   : SSP1EN SPI(pass), I2C(1 = enable SDA\/SCL w\/input mode, 0 = disable)\r\n\t\/\/ bit4   : CKP    SPI(pass), I2C(master(1 = enable clock, 0 = hold clock low), slave (unused))\r\n\t\/\/ bit3-0 : SSP1M  0110 I2C Slave mode, 7bit address\r\n\t\/\/        : SSP1M  0111 I2C Slave mode, 10bit address\r\n\t\/\/        : SSP1M  1000 I2C Master mode, clock = Fosc\/(4 * (SSP1ADD + 1))\r\n\t\/\/        : SSP1M  1011 I2C F\/W controled Master mode(Slave Idle)\r\n\t\/\/        : SSP1M  1110 I2C Slave mode, 7bit address w\/Start\/Stop bit INT\r\n\t\/\/        : SSP1M  1111 I2C Slave mode, 10bit address w\/Start\/Stop bit INT\r\n\tSSP1CON1 = 0b00110110;\t\t\/\/ SSP1EN = 1, CKP = 1, SSP1M = Slave mode 7bit \r\n\t\r\n\tSSP1CON2bits.SEN = 1;\t\t\/\/ Start Condition Enabled bit ... SSP1CON2) \u2190\u30de\u30b9\u30bf\u30fc\u304b\u3089\u30c7\u30fc\u30bf\u3092\u53d7\u3051\u53d6\u308b\u306a\u3089\u8a2d\u5b9a\u5fc5\u8981\r\n\t\r\n\t\/\/ \u3053\u306e\u30c7\u30d0\u30a4\u30b9\u306eI2C\u30a2\u30c9\u30ec\u30b9\u3092\u8a2d\u5b9a\r\n\tSSP1ADD = I2C_ADDR << 1;\r\n\t\r\n\t\/\/ MSSP1\u5272\u308a\u8fbc\u307f\u521d\u671f\u5316\r\n\tPIR1bits.SSP1IF = 0;\r\n\t\r\n\t\/\/ MSSP1\u30d0\u30b9\u885d\u7a81\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u3092\u521d\u671f\u5316\r\n\tPIR2bits.BCL1IF = 0;\r\n\t\r\n\t\/\/ 100ms\u5f85\u3064\r\n\tDelay_10ms(10);\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ Setup Timer 18F26K22\r\n\/\/ ------------------------------\r\nvoid init_timer_18F26K22(void)\r\n{\r\n\t\/\/ \u5272\u308a\u8fbc\u307f\u51e6\u7406\u5185\u3067\u30d3\u30c3\u30c8\u30b7\u30d5\u30c8\u3068\u304b\u3042\u308c\u304b\u306a\uff1f\u3068\u601d\u3063\u3066\u3053\u3053\u3067\u4e88\u3081\u4f5c\u3063\u3066\u304a\u304f\u3053\u3068\u306b\u3059\u308b\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u30bf\u30a4\u30e0\u30a2\u30a6\u30c8\u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\ttimer0_h = (TIMER_100ms >> 8);\r\n\ttimer0_l = (TIMER_100ms & 0x00ff);\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u7528\u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\ttimer1_h = (TIMER_80us >> 8);\r\n\ttimer1_l = (TIMER_80us & 0x00ff);\r\n\t\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ Interrupt Routine\r\n\/\/ ------------------------------\r\n\/\/ I2C\u306e\u30de\u30b9\u30bf\u30fc\u3068\u30b9\u30ec\u30fc\u30d6\u3068\u306e\u3084\u308a\u53d6\u308a\u306f\u3001\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u306e\u8aac\u660e\u304c\u8a00\u8449\u8db3\u3089\u305a\u306a\u305f\u3081\u306b\r\n\/\/ \u975e\u5e38\u306b\u5224\u308a\u3065\u3089\u3044\u3002\u305f\u3060\u3057\u3001\u5224\u3063\u3066\u3057\u307e\u3046\u3068\u4f55\u3060\u305d\u308c\u3060\u3051\u304b\u3001\u3068\u306a\u308b\u3002\r\n\/\/ \r\n\/\/ \u7279\u306b\u30b9\u30ec\u30fc\u30d6\u5074\u3067\u3042\u308c\u3053\u308c\u8a2d\u5b9a\u3057\u305f\u308a\u5224\u5b9a\u3084\u51e6\u7406\u306b\u5fc5\u8981\u306a\u306e\u306f\u6b21\u306e\u30d3\u30c3\u30c8\r\n\/\/ \u30fbD\/A\u20261=SSP1BUF\u306e\u4e2d\u306f\u30c7\u30fc\u30bf\u30010=SSP1BUF\u306e\u4e2d\u306f\u30a2\u30c9\u30ec\u30b9(\u7a7a\u3063\u307d\u2026\u7a7a\u306e\u8aad\u307f\u51fa\u3057\u8981\u6c42\u6642)\r\n\/\/ \u30fbR\/W\u20261=\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u53d7\u4fe1\u30010=\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u3078\u9001\u4fe1\r\n\/\/ \u30fbBF\u20261=\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u5165\u3063\u3066\u3044\u308b(\u7a7a\u306e\u8aad\u307f\u51fa\u3057\u8981\u6c42\u6642\u3082)\u30010=\u30d0\u30c3\u30d5\u30a1\u306f\u7a7a\u3063\u307d\r\n\/\/ \u30fbCKP\u2026\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\u3068\u304d\u3001\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u9001\u4fe1\u3059\u308b\u3068\u304d\u306b1\u306b\u3057\u3066SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3059\u308b\r\n\/\/ \u30fbSSP1IF\u2026\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u3001\u306a\u3093\u304b\u3057\u305f\u3089\u30af\u30ea\u30a2\u3059\u308b\r\n\/\/ \u30fbSEN\u2026\u30de\u30b9\u30bf\u30fc\u304b\u3089\u30c7\u30fc\u30bf\u3092\u53d7\u4fe1\u3059\u308b\u6642\u306b\u3001\u30bd\u30d5\u30c8\u5074\u3067CKP\u3092\u5236\u5fa1\u3059\u308b\u305f\u3081\u306b1\u306b\u3059\u308b\u30020\u3060\u3068\u3046\u307e\u304f\u52d5\u304b\u306a\u3044\u3088!!\r\n\/\/(\u30fbS\u2026\u30b9\u30bf\u30fc\u30c8\u30d3\u30c3\u30c8\u3001\u7279\u306b\u4f7f\u308f\u306a\u304f\u3066\u3082\u3044\u3044\u6c17\u304c\u3059\u308b)\r\n\/\/\r\n\/\/ \u3067\u3001\u5224\u5b9a\u306b\u4f7f\u3046\u30d3\u30c3\u30c8\u304c\u591a\u3044\u3051\u3069\u3001\u57fa\u672c\u7684\u306b\u306fSSP1STAT\u306a\u306e\u3067\u3001\u30de\u30b9\u30af\u3057\u3066\u4e00\u62ec\u5224\u5b9a\u3059\u308c\u3070OK\u3002\r\n\/\/ \r\n\/\/ \u8d64\u5916\u7dda\u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3067\u306f\u3001\u9001\u4fe1\u7528\u306e\u5272\u308a\u8fbc\u307f\u304c\u6765\u305f\u3089\u3068\u308a\u3042\u3048\u305a\u3059\u3050\u306b\u51fa\u529b\u3092\u5909\u66f4\u3057\u3066\u304b\u3089\u3001\u6b21\u306e\u30c7\u30fc\u30bf\u306e\r\n\/\/ \u8a2d\u5b9a\u306a\u3069\u3092\u3059\u308b\u3002\u6b21\u306e\u5272\u308a\u8fbc\u307f\u307e\u3067\u306f80us\u3057\u304b\u306a\u3044(\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u9593\u9694\u3092\u77ed\u304f\u3057\u305f\u3089\u3082\u3063\u3068\u5c11\u306a\u3044)\u306e\u3067\u3001\u51e6\u7406\u306f\u6975\u529b\r\n\/\/ \u5358\u7d14\u306b\u3057\u3066\u77ed\u6642\u9593\u3067\u6e08\u307e\u3059\u3088\u3046\u306b\u3059\u308b\u3053\u3068\r\n\/\/ \r\n\/\/ --------------------------------------------------\r\n\/\/ 18F26K22 Interrupt Routine\r\n\/\/ --------------------------------------------------\r\n\/\/ \u5272\u308a\u8fbc\u307f\u306f\u3059\u3079\u3066interrupt\u5ba3\u8a00\u3055\u308c\u305f\u3053\u306e\u95a2\u6570\u304c\u547c\u3070\u308c\u308b\r\nstatic void interrupt interrupt_18F26K22()\r\n{\r\n\t\/\/ \u5168\u5272\u308a\u8fbc\u307f\u3092\u7981\u6b62(=0) (Global Interrupt Enable bit ... INTCON)\r\n\tINTCONbits.GIE = 0;\r\n\t\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u8aad\u307f\u53d6\u308a\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u30bf\u30a4\u30de\u30fc or \u9001\u4fe1\u7528\u30bf\u30a4\u30de\u30fc\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u5272\u308a\u8fbc\u307f(=1)\u306a\u3089 (Timer1 Overflow Interrupt Flag bit ... PIR1)\r\n\tif (PIR1bits.TMR1IF == 1)\r\n\t{\r\n\t\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30ab\u30a6\u30f3\u30bf\u3092\u52a0\u7b97\r\n\t\ttimer1_count ++;\r\n\t\t\r\n\t\t\/\/ \u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\t\tTMR1H = timer1_h;\r\n\t\tTMR1L = timer1_l;\r\n\t\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u521d\u671f\u5316\r\n\t\tPIR1bits.TMR1IF = 0;\r\n\t\t\r\n\t\t\/\/ \u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u30bf\u30a4\u30de\u30fc\u30ab\u30a6\u30f3\u30bf\u304c1\u56de\u306b\u306a\u3063\u305f\u3089\r\n\t\tif (timer1_count >= 1)\r\n\t\t{\r\n\t\t\t\/\/ ----------------------------------------\r\n\t\t\t\/\/ \u3082\u3057\u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0\u304c\u53d7\u4fe1\u4e2d\u306a\u3089\r\n\t\t\t\/\/ ----------------------------------------\r\n\t\t\tif (ir_trx_flag == 1)\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u3092\u53d6\u5f97\r\n\t\t\t\tir_data = PORT_IR_RX;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u304c\u53d7\u4fe1\u5f85\u3061(1)\u306a\u3089\r\n\t\t\t\tif (ir_rx_status == 1)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3068ir_data\u304c\u540c\u3058\u3067\u306a\u3044\u306a\u3089\r\n\t\t\t\t\tif (ir_data != ir_status)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u4e2d(2)\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tir_rx_status = 2;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u304c\u53d7\u4fe1\u4e2d\u306a\u3089\r\n\t\t\t\tif (ir_rx_status == 2)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u304c1\u306a\u3089\r\n\t\t\t\t\tif (ir_data == 1)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u306b1\u3092\u7acb\u3066\u3066(\u8db3\u3057\u7b97\u3067OK)\u3001\u30d3\u30c3\u30c8\u30de\u30b9\u30af\u7d50\u679c\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\t*ir_buffer += ir_bit;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u3092\u5de6\u30b7\u30d5\u30c8(\u3064\u307e\u308a+1)\r\n\t\t\t\t\tir_bit <<= 1;\r\n\t\t\t\t\tir_bit &= 0xff;\r\n\t\t\t\t\t\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u304c\u30aa\u30fc\u30d0\u30fc\u30d5\u30ed\u30fc\u3057\u305f\u3089\r\n\t\t\t\t\tif (ir_bit == 0)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u3092\u30af\u30ea\u30a2\r\n\t\t\t\t\t\tir_bit = 1;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30dd\u30a4\u30f3\u30bf\u3092\u52a0\u7b97\r\n\t\t\t\t\t\tir_buffer ++;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\u3092+1\r\n\t\t\t\t\t\tir_count ++;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\u304cIR_BUFF_SIZE\u306b\u306a\u3063\u305f\u3089\u3000\u2605\u5b9f\u969b\u306e\u683c\u7d0d\u4f4d\u7f6e\u306b\u6ce8\u610f\r\n\t\t\t\t\tif (ir_count == IR_BUFF_SIZE)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9577\u3092\u8a2d\u5b9a\r\n\t\t\t\t\t\tir_data_len = ir_count;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u30a8\u30e9\u30fc(-99:\u30d0\u30c3\u30d5\u30a1\u30aa\u30fc\u30d0\u30fc\u30d5\u30ed\u30fc)\u306b\r\n\t\t\t\t\t\tir_rx_status = -99;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u6d88\u706f\r\n\t\t\t\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t\t\t\t\t\/\/ \u30b9\u30c6\u30fc\u30bf\u30b9LED\u3092\u6d88\u706f\r\n\t\t\t\t\t\tPORT_STATUS_LED = LED_OFF;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u6700\u5927\u53d7\u4fe1\u30e2\u30fc\u30c9\u304c\u901a\u5e38(=0)\u306a\u3089\r\n\t\t\t\t\t\tif (ir_rxmax == 0)\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\/\/ \u2605\u5272\u308a\u8fbc\u307f\u51e6\u7406\u3092\u629c\u3051\u3066\u3001\u5225\u9014\u30a8\u30e9\u30fc\u51e6\u7406\r\n\t\t\t\t\t\t\treturn;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u6700\u5927\u53d7\u4fe1\u30e2\u30fc\u30c9\u304c\u6700\u5927(=1)\u306a\u3089\r\n\t\t\t\t\t\telse if (ir_rxmax == 1)\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u5b8c\u4e86(99)\u306b\r\n\t\t\t\t\t\t\tir_rx_status = 99;\r\n\t\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\t\t\t\tir_buffer = gvc_i2c_message->data;\r\n\t\t\t\t\t\t\t\/\/ \u5f85\u907f\u30d0\u30c3\u30d5\u30a1\u306b\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u3092\u30b3\u30d4\u30fc\r\n\t\t\t\t\t\t\tir_saved_buffer[1] = ir_buffer[1];\r\n\t\t\t\t\t\t\tir_saved_buffer[2] = ir_buffer[2];\r\n\t\t\t\t\t\t\tir_saved_buffer[3] = ir_buffer[3];\r\n\t\t\t\t\t\t\tir_saved_buffer[4] = ir_buffer[4];\r\n\t\t\t\t\t\t\tir_saved_buffer[5] = ir_buffer[5];\r\n\t\t\t\t\t\t\tir_saved_buffer[6] = ir_buffer[6];\r\n\t\t\t\t\t\t\tir_saved_buffer[7] = ir_buffer[7];\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u304c\u540c\u3058\u3067\u3042\u308a\u3001\u30ea\u30e2\u30b3\u30f3\u6700\u5927\u53d7\u4fe1\u30e2\u30fc\u30c9\u304c\u901a\u5e38(=0)\u306a\u3089\r\n\t\t\t\t\tif ((ir_data == ir_status) && (ir_rxmax == 0))\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf++\r\n\t\t\t\t\t\tir_same_count ++;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf\u304c10ms(50us\u306e\u5834\u5408\u306b\u306f200\u300180us\u306e\u5834\u5408\u306b\u306f125)\u7d9a\u3044\u305f\u3089\u3000\u2190\u30bd\u30cb\u30fc\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u3067\u3044\u307e\u3044\u3061\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf\u304c20ms(50us\u306e\u5834\u5408\u306b\u306f400\u300180us\u306e\u5834\u5408\u306b\u306f250)\u7d9a\u3044\u305f\u3089\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf\u304c30ms(50us\u306e\u5834\u5408\u306b\u306f600\u300180us\u306e\u5834\u5408\u306b\u306f375)\u7d9a\u3044\u305f\u3089\u3000\u2190\u540c\u4e00\u4fe1\u53f7\u306e\u518d\u9001\u4fe1\u306b\u304b\u304b\u308b\u3053\u3068\u304c\u3042\u308b\r\n\t\t\t\t\t\t\/\/ \u2026\u3069\u3046\u3082\u3046\u3061\u306e\u30ea\u30e2\u30b3\u30f3\u306f\u3044\u3063\u3071\u3044\u9001\u3063\u3066\u3044\u308b\u306e\u3067\u306f\uff1f\u3068\u601d\u3063\u3066\u3001\u7d42\u4e86\u5224\u5b9a\u3092\u9577\u3081\u306b\u3057\u3066\u307f\u305f\u3002\r\n\t\t\t\t\t\t\/\/ \u3053\u308c\u3067\u3082\u30c0\u30e1\u306a\u3089\u3001\u3084\u306f\u308a\u30b9\u30c8\u30ec\u30fc\u30b8\u30aa\u30b7\u30ed\u304b\u4f55\u304b\u3067\u30ea\u30e2\u30b3\u30f3\u6ce2\u5f62\u3092\u898b\u306a\u304c\u3089\u51fa\u306a\u3044\u3068\u306d\u30022013.07.31 T.Kabu\r\n\t\t\t\t\t\tif (ir_same_count > 250)\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9577\u3092\u8a2d\u5b9a\r\n\t\t\t\t\t\t\tir_data_len = ir_count;\r\n\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u5b8c\u4e86(99)\u306b\r\n\t\t\t\t\t\t\tir_rx_status = 99;\r\n\t\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\t\t\t\tir_buffer = gvc_i2c_message->data;\r\n\t\t\t\t\t\t\t\/\/ \u5f85\u907f\u30d0\u30c3\u30d5\u30a1\u306b\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u3092\u30b3\u30d4\u30fc\r\n\t\t\t\t\t\t\tir_saved_buffer[1] = ir_buffer[1];\r\n\t\t\t\t\t\t\tir_saved_buffer[2] = ir_buffer[2];\r\n\t\t\t\t\t\t\tir_saved_buffer[3] = ir_buffer[3];\r\n\t\t\t\t\t\t\tir_saved_buffer[4] = ir_buffer[4];\r\n\t\t\t\t\t\t\tir_saved_buffer[5] = ir_buffer[5];\r\n\t\t\t\t\t\t\tir_saved_buffer[6] = ir_buffer[6];\r\n\t\t\t\t\t\t\tir_saved_buffer[7] = ir_buffer[7];\r\n\t\t\t\t\t\t\t\/\/ LED\u3092\u70b9\u706f\u3057\u3063\u3071\u306a\u3057\u306b\r\n\t\t\t\t\t\t\tPORT_RESULT_LED = LED_ON;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ \u305d\u3046\u3067\u306f\u306a\u3044\u306a\u3089\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf\u3092\u30ea\u30bb\u30c3\u30c8\r\n\t\t\t\t\t\tir_same_count = 0;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u304c\u53d7\u4fe1\u4e2d\u306a\u3089\r\n\t\t\t\tif (ir_rx_status == 2)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u3092\u6b21\u3068\u306e\u6bd4\u8f03\u306e\u305f\u3081\u306b\u8a2d\u5b9a\r\n\t\t\t\t\tir_status = ir_data;\r\n\t\t\t\t}\r\n\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30ab\u30a6\u30f3\u30bf\u30fc\u30ea\u30bb\u30c3\u30c8\r\n\t\t\t\ttimer1_count = 0;\r\n\t\t\t}\r\n\t\t\t\/\/ ----------------------------------------\r\n\t\t\t\/\/ \u3082\u3057\u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0\u304c\u9001\u4fe1\u4e2d\u306a\u3089\r\n\t\t\t\/\/ ----------------------------------------\r\n\t\t\tif (ir_trx_flag == 2)\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u8d64\u5916\u7ddaLED\u306e\u70b9\u706f\u306f\u3001\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u30c7\u30fc\u30bf\u30681\/0\u53cd\u8ee2\u3055\u305b\u308b\u3053\u3068!!\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u4fe1\u30d3\u30c3\u30c8\u306b\u57fa\u3065\u3044\u3066PSTR1CON\u3092\u8a2d\u5b9a\r\n\t\t\t\t\/\/ \u9001\u4fe1\u30c7\u30fc\u30bf\u304c0\u306a\u3089\r\n\t\t\t\tif (ir_tx_data == 0)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ PSTR1CON \u3092\u8a2d\u5b9a(\u9001\u4fe1)\r\n\t\t\t\t\tPSTR1CON = 0b00010001;\t\/\/ STR1SYNC = 1, STR1A = 1;\r\n\t\t\t\t}\r\n\t\t\t\t\/\/ \u9001\u4fe1\u30c7\u30fc\u30bf\u304c1\u306a\u3089\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ PSTR1CON \u3092\u8a2d\u5b9a(\u505c\u6b62)\r\n\t\t\t\t\tPSTR1CON = 0b00010000;\t\/\/ STR1SYNC = 1, STR1A = 0;\r\n\t\t\t\t}\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u3092\u5de6\u30b7\u30d5\u30c8(\u3064\u307e\u308a+1)\r\n\t\t\t\tir_bit <<= 1;\r\n\t\t\t\tir_bit &= 0xff;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u304c\u30aa\u30fc\u30d0\u30fc\u30d5\u30ed\u30fc\u3057\u305f\u3089\r\n\t\t\t\tif (ir_bit == 0)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u3092\u30af\u30ea\u30a2\r\n\t\t\t\t\tir_bit = 1;\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30dd\u30a4\u30f3\u30bf\u3092\u52a0\u7b97\r\n\t\t\t\t\tir_buffer ++;\r\n\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\u3092+1\r\n\t\t\t\t\tir_count ++;\r\n\t\t\t\t}\r\n\t\t\t\t\/\/ \u6b21\u306e\u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u30d3\u30c3\u30c8\u3092\u8a2d\u5b9a(\u9001\u4fe1\u30d0\u30a4\u30c8\u3068\u9001\u4fe1\u5bfe\u8c61\u30d3\u30c3\u30c8\u3092AND\u3057\u305f\u5024)\r\n\t\t\t\tir_tx_data = *ir_buffer & ir_bit;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u4fe1\u30c7\u30fc\u30bf\u306e\u6700\u5f8c\u307e\u3067\u884c\u3063\u305f\u3089\r\n\t\t\t\tif (ir_buffer == ir_buffer_end)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ \u8d64\u5916\u7dda\u9001\u4fe1\u56de\u6570\u3092\u52a0\u7b97\r\n\t\t\t\t\tir_tx_count ++;\r\n\t\t\t\t\t\r\n\t\t\t\t\t\/\/ \u8d64\u5916\u7dda\u9001\u4fe1\u56de\u6570\u304c\u898f\u5b9a\u5024\u3092\u8d85\u3048\u305f\u3089\r\n\t\t\t\t\tif (ir_tx_count > IR_TX_MAX)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9001\u4fe1\u30bf\u30a4\u30de\u30fc\u505c\u6b62\r\n\t\t\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\t\t\tT1CON &= 0b11111110;\r\n\t\t\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9001\u4fe1\u7528PWM\u505c\u6b62\r\n\t\t\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\t\t\t\/\/ PWM\u7528\u30bf\u30a4\u30de\u30fc(TIMER2)\u3092\u505c\u6b62(\u8a73\u3057\u304f\u306f\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u53c2\u7167)\r\n\t\t\t\t\t\tT2CON &= 0b11111011;\r\n\t\t\t\t\t\t\/\/ PSTR1CON \u3092\u8a2d\u5b9a(\u505c\u6b62)\r\n\t\t\t\t\t\tPSTR1CON = 0b00000000;\t\/\/ STR1SYNC = 1, STR1A = 0;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0\u3092\u9001\u53d7\u4fe1\u7121\u3057(=0)\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tir_trx_flag = 0;\r\n\t\t\t\t\t\t\/\/ \u9001\u4fe1\u958b\u59cbLED\u6d88\u706f\r\n\t\t\t\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ \u307e\u3060\u9001\u4fe1\u3057\u306a\u3051\u308c\u3070\u306a\u3089\u306a\u3044\u306a\u3089\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\t\t\tir_buffer = gvc_i2c_message->data;\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\u306e\u521d\u671f\u5316\r\n\t\t\t\t\t\tir_count = 0;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u306e\u521d\u671f\u5316\r\n\t\t\t\t\t\tir_bit = 1;\r\n\t\t\t\t\t\t\/\/ \u521d\u56de\u306e\u9001\u4fe1\u30d3\u30c3\u30c8\u3092\u8a2d\u5b9a(\u9001\u4fe1\u30d0\u30a4\u30c8\u3068\u9001\u4fe1\u5bfe\u8c61\u30d3\u30c3\u30c8\u3092AND\u3057\u305f\u5024)\r\n\t\t\t\t\t\tir_tx_data = *ir_buffer & ir_bit;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30ab\u30a6\u30f3\u30bf\u30fc\u30ea\u30bb\u30c3\u30c8\r\n\t\t\t\ttimer1_count = 0;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\t\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ 100ms\u9593\u9694\u30bf\u30a4\u30de\u30fc\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc0\u5272\u308a\u8fbc\u307f(=1)\u306a\u3089 (Timer0 Overflow Interrupt Flag bit ... INTCON)\r\n\tif (INTCONbits.TMR0IF == 1)\r\n\t{\r\n\t\t\/\/ \u30bf\u30a4\u30de\u30fc0\u30ab\u30a6\u30f3\u30bf\u3092\u52a0\u7b97\r\n\t\ttimer0_count ++;\r\n\t\t\r\n\t\t\/\/ \u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\t\tTMR0H = timer0_h;\r\n\t\tTMR0L = timer0_l;\r\n\t\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u521d\u671f\u5316\r\n\t\tINTCONbits.TMR0IF = 0;\r\n\t\t\r\n\t\t\/\/ \u3082\u3057\u30ab\u30a6\u30f3\u30bf\u304c50\u56de(=5s)\u306b\u306a\u3063\u305f\u3089\r\n\t\tif (timer0_count >= 50)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0\u304c\u53d7\u4fe1\u4e2d(=1)\u306a\u3089\u2192\u53d7\u4fe1\u7d42\u4e86\r\n\t\t\tif (ir_trx_flag == 1)\r\n\t\t\t{\r\n\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u8aad\u307f\u53d6\u308a\u30bf\u30a4\u30e0\u30a2\u30a6\u30c8\u30bf\u30a4\u30de\u30fc\u505c\u6b62\r\n\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\tT0CON &= 0b01111111;\r\n\t\t\t\t\/\/ \u30b9\u30c6\u30fc\u30bf\u30b9LED\u3092OFF\r\n\t\t\t\tPORT_STATUS_LED = LED_OFF;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u53d7\u4fe1\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u30bf\u30a4\u30de\u30fc\u505c\u6b62\r\n\t\t\t\t\/\/ ------------------------------\r\n\t\t\t\tT1CON &= 0b11111110;\r\n\t\t\t\t\/\/ \u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u30bf\u30a4\u30de\u30fc\u306e\u30ea\u30b6\u30eb\u30c8LED\u3082OFF\u306b\r\n\t\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30bf\u30a4\u30de\u30fc0\u30ab\u30a6\u30f3\u30bf\u30fc\u30ea\u30bb\u30c3\u30c8\r\n\t\t\t\ttimer0_count = 0;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u5b8c\u4e86(99)\u306b\r\n\t\t\t\tir_rx_status = 99;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0\u3092\u9001\u53d7\u4fe1\u7121\u3057(=0)\u306b\u8a2d\u5b9a\r\n\t\t\t\tir_trx_flag = 0;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\t\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ MSSP1\u5272\u308a\u8fbc\u307f\u51e6\u7406 (Rev.1\u306e18F26K22_I2C.c\u3092\u53c2\u7167\u3059\u308b\u3053\u3068\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ MSSP\u5272\u308a\u8fbc\u307f(=1)\u306a\u3089 (Synchronous Serial Port (MSSP) Interrupt Flag bit ... PIR1)\r\n\tif (PIR1bits.SSP1IF == 1)\r\n\t{\r\n\t\t\/\/ \u30b9\u30c6\u30fc\u30bf\u30b9LED\u3092\u70b9\u706f\r\n\t\tPORT_STATUS_LED = LED_ON;\r\n\t\t\r\n\t\t\/\/ MSSP\u5272\u308a\u8fbc\u307f\u30af\u30ea\u30a2(=0) (Synchronous Serial Port (MSSP) Interrupt Flag bit ... PIR1)\r\n\t\tPIR1bits.SSP1IF = 0;\r\n\t\t\r\n\t\t\/\/ SSP1\u30b9\u30c6\u30fc\u30bf\u30b9\u3092\u53d6\u5f97\u3001D\/A\u3001R\/W\u3001BF\u30d3\u30c3\u30c8\u3092\u30de\u30b9\u30af\r\n\t\treg_SSP1STAT = SSP1STAT & 0b00100101;\r\n\t\t\r\n\t\t\/\/ SSP1\u30b9\u30c6\u30fc\u30bf\u30b9\u304c\u3001\u30a2\u30c9\u30ec\u30b9(D\/A=0)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u3078\u9001\u4fe1(R\/W=0)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u3042\u308b(BF=1)\u306a\u3089\r\n\t\tif (reg_SSP1STAT == 0b00000001)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u70b9\u706f\r\n\t\t\tPORT_RESULT_LED = LED_ON;\r\n\t\t\t\r\n\t\t\t\/\/ SSP1BUF\u3092\u7a7a\u8aad\u307f\u3057\u3066\r\n\t\t\ttemp_buffer = SSP1BUF;\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092\u521d\u671f\u5316\r\n\t\t\trx_count = 0;\r\n\t\t\t\r\n\t\t\t\/\/ I2C\u30b9\u30c6\u30fc\u30bf\u30b9 0:\u5f85\u6a5f\u72b6\u614b 1:\u30c7\u30fc\u30bf\u53d7\u4fe1\u4e2d 10:\u30c7\u30fc\u30bf\u53d7\u4fe1\u5b8c\u4e86\r\n\t\t\ti2c_status = 1;\r\n\t\t\t\r\n\t\t\t\/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n\t\t\tSSP1CON1bits.CKP1 = 1;\r\n\t\t\t\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u6d88\u706f\r\n\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t}\r\n\t\t\/\/ SSP1\u30b9\u30c6\u30fc\u30bf\u30b9\u304c\u3001\u30c7\u30fc\u30bf(D\/A=1)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u3078\u9001\u4fe1(R\/W=0)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u3042\u308b(BF=1)\u306a\u3089\r\n\t\telse if (reg_SSP1STAT == 0b00100001)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u70b9\u706f\r\n\t\t\tPORT_RESULT_LED = LED_ON;\r\n\t\t\t\r\n\t\t\t\/\/ SSP1BUF\u304b\u3089\u30c7\u30fc\u30bf\u3092\u8aad\u307f\u51fa\u3057\u3066\u3001\u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u306e\u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u306b\u8a2d\u5b9a\r\n\t\t\tmain_buffer[rx_count] = SSP1BUF;\r\n\t\t\t\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u304c3\u307e\u3067\u6765\u3066\u305f\u3089\r\n\t\t\tif (rx_count == 3)\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u3053\u306e\u3042\u3068\u53d7\u4fe1\u3059\u308b\u30c7\u30fc\u30bf\u9577\u3092\u8a2d\u5b9a\r\n\t\t\t\ti2c_data_len = *(int *)(main_buffer + 2);\r\n\t\t\t}\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u304cchecksum(\u3064\u307e\u308a\u30e1\u30c3\u30bb\u30fc\u30b8\u7d42\u4e86)\u306a\u3089\r\n\t\t\tif (rx_count == (GVC_I2C_MESSAGE_HEADER_SIZE + i2c_data_len))\r\n\t\t\t{\r\n\t\t\t\t\/\/ --------------------------------------------------------------------------------\r\n\t\t\t\t\/\/ \u5fc5\u8981\u306a\u3089\u30e1\u30c3\u30bb\u30fc\u30b8\u53d7\u4fe1\u3057\u305f\u3088\u30d5\u30e9\u30b0\u3067\u3082\u7acb\u3066\u3066\u30e1\u30a4\u30f3\u30eb\u30fc\u30d7\u5185\u3067\u51e6\u7406\u3057\u3066\u3082\u3089\u3046\r\n\t\t\t\t\/\/ --------------------------------------------------------------------------------\r\n\t\t\t\t\/\/ I2C\u30b9\u30c6\u30fc\u30bf\u30b9 0:\u5f85\u6a5f\u72b6\u614b 1:\u30c7\u30fc\u30bf\u53d7\u4fe1\u4e2d 10:\u30c7\u30fc\u30bf\u53d7\u4fe1\u5b8c\u4e86\r\n\t\t\t\ti2c_status = 10;\r\n\t\t\t\t\r\n\t\t\t\t\/\/ \r\n\t\t\t\t\/\/ \u30fb\u30e1\u30c3\u30bb\u30fc\u30b8\u30c7\u30fc\u30bf\u306eCRC\u3092\u691c\u67fb\r\n\t\t\t\t\/\/ \u30fbOK\u306a\u3089\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u3084\u30b3\u30de\u30f3\u30c9\u306b\u57fa\u3065\u3044\u3066\u51e6\u7406\u3001NG\u306a\u3089\u30b7\u30ea\u30a2\u30eb\u306b\u305d\u306e\u65e8\u51fa\u529b\r\n\t\t\t\t\/\/ \r\n\t\t\t\t\/\/ CRC\u30c1\u30a7\u30c3\u30af\u304cOK\u306a\u3089\r\n\t\t\t\tif (GetCRC8((void *)main_buffer, rx_count + 1) == 0)\r\n\t\t\t\t{\r\n\t\t\t\t\t\/\/ \u30b5\u30d6\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)sub_buffer;\r\n\t\t\t\t\tgvc_i2c_message->format = main_buffer[0];\t\t\/\/ \u30de\u30b9\u30bf\u30fc\u304b\u3089\u306e\u8981\u6c42\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u3092\u305d\u306e\u307e\u307e\u8fd4\u3059\r\n\t\t\t\t\tgvc_i2c_message->cmd = main_buffer[1];\t\t\/\/ \u30a8\u30e9\u30fc\u306e\u5834\u5408\u306b\u306f\u3053\u3053\u3092\u9055\u3046\u30c7\u30fc\u30bf\u306b\u3059\u308b\u306e\u304c\u3044\u3044\u3068\u601d\u3046\u2026TBD\r\n\t\t\t\t\t\/\/ \u8981\u6c42\u30b3\u30de\u30f3\u30c9\u304c0x91\u306a\u3089\r\n\t\t\t\t\tif (main_buffer[1] == 0x91)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9001\u4fe1\u8981\u6c42\r\n\t\t\t\t\t\tsprintf(gvc_i2c_message->data, "IR TX");\r\n\t\t\t\t\t\tgvc_i2c_message->data_len = strlen(gvc_i2c_message->data);\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u518d\u9001\u4fe1\u30e2\u30fc\u30c9(=2)\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tir_mode = 2;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ \u8981\u6c42\u30b3\u30de\u30f3\u30c9\u304c0x92\u306a\u3089\r\n\t\t\t\t\telse if (main_buffer[1] == 0x92)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u53d7\u4fe1\u8981\u6c42\r\n\t\t\t\t\t\tsprintf(gvc_i2c_message->data, "IR RX");\r\n\t\t\t\t\t\tgvc_i2c_message->data_len = strlen(gvc_i2c_message->data);\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u8aad\u307f\u53d6\u308a\u30e2\u30fc\u30c9(=1)\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tir_mode = 1;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ \u8981\u6c42\u30b3\u30de\u30f3\u30c9\u304c0x93\u306a\u3089\r\n\t\t\t\t\telse if (main_buffer[1] == 0x93)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tsend_strdata("--- IR SET REQUEST ---");\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u5b8c\u4e86(99)\u306b\u3059\u308b\r\n\t\t\t\t\t\tir_rx_status = 99;\r\n\t\t\t\t\t\t\/\/ \u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u306e\u30c7\u30fc\u30bf\u9577\u3092\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\t\t\tir_data_len = gvc_i2c_message->data_len;\r\n\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\t\t\tir_buffer = gvc_i2c_message->data;\r\n\t\t\t\t\t\t\/\/ \u5f85\u907f\u30d0\u30c3\u30d5\u30a1\u306b\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u3092\u30b3\u30d4\u30fc\r\n\t\t\t\t\t\tir_saved_buffer[0] = ir_buffer[0];\r\n\t\t\t\t\t\tir_saved_buffer[1] = ir_buffer[1];\r\n\t\t\t\t\t\tir_saved_buffer[2] = ir_buffer[2];\r\n\t\t\t\t\t\tir_saved_buffer[3] = ir_buffer[3];\r\n\t\t\t\t\t\tir_saved_buffer[4] = ir_buffer[4];\r\n\t\t\t\t\t\tir_saved_buffer[5] = ir_buffer[5];\r\n\t\t\t\t\t\tir_saved_buffer[6] = ir_buffer[6];\r\n\t\t\t\t\t\tir_saved_buffer[7] = ir_buffer[7];\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\/\/ \u30b5\u30d6\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)sub_buffer;\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u8a2d\u5b9a\u8981\u6c42\r\n\t\t\t\t\t\tsprintf(gvc_i2c_message->data, "IR SET, ir_data_len=%d", ir_data_len);\r\n\t\t\t\t\t\tgvc_i2c_message->data_len = strlen(gvc_i2c_message->data);\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tsend_strdata("DATA LENGTH = ");\r\n\t\t\t\t\t\tsend_intdata(ir_data_len);\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t\tsend_strdata("STATUS = ");\r\n\t\t\t\t\t\tsend_intdata(ir_rx_status);\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t\tsend_strdata("--- IR SET END ---");\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ \u8981\u6c42\u30b3\u30de\u30f3\u30c9\u304c0x94\u306a\u3089\r\n\t\t\t\t\telse if (main_buffer[1] == 0x94)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tsend_strdata("--- IR GET REQUEST ---");\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t\tsend_strdata("DATA LENGTH = ");\r\n\t\t\t\t\t\tsend_intdata(ir_data_len);\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t\tsend_strdata("STATUS = ");\r\n\t\t\t\t\t\tsend_intdata(ir_rx_status);\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u304c\u53d7\u4fe1\u5b8c\u4e86(99)\u306a\u3089\r\n\t\t\t\t\t\tif (ir_rx_status == 99)\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u3092\u6271\u3046\u3068\u304d\u306b\u306f\u3001\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u3092main_buffer\u306b\u5207\u308a\u66ff\u3048\u306a\u3044\u3068\u3044\u3051\u306a\u3044\r\n\t\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\t\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\t\t\t\t\t\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\t\t\t\tir_buffer = gvc_i2c_message->data;\r\n\t\t\t\t\t\t\t\/\/ \u5f85\u907f\u30d0\u30c3\u30d5\u30a1\u304b\u3089\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u3092\u30b3\u30d4\u30fc\r\n\t\t\t\t\t\t\tir_buffer[0] = ir_saved_buffer[0];\r\n\t\t\t\t\t\t\tir_buffer[1] = ir_saved_buffer[1];\r\n\t\t\t\t\t\t\tir_buffer[2] = ir_saved_buffer[2];\r\n\t\t\t\t\t\t\tir_buffer[3] = ir_saved_buffer[3];\r\n\t\t\t\t\t\t\tir_buffer[4] = ir_saved_buffer[4];\r\n\t\t\t\t\t\t\tir_buffer[5] = ir_saved_buffer[5];\r\n\t\t\t\t\t\t\tir_buffer[6] = ir_saved_buffer[6];\r\n\t\t\t\t\t\t\tir_buffer[7] = ir_saved_buffer[7];\r\n\t\t\t\t\t\t\t\/\/ \u30d5\u30a9\u30fc\u30de\u30c3\u30c8\u3092\u30d0\u30a4\u30ca\u30ea\u30c7\u30fc\u30bf\u3068\u3057\u3066\u8a2d\u5b9a\r\n\t\t\t\t\t\t\tgvc_i2c_message->format = 0x31;\t\t\t\t\/\/ \u30c7\u30fc\u30bf\u30d5\u30a9\u30fc\u30de\u30c3\u30c8\r\n\t\t\t\t\t\t\tgvc_i2c_message->cmd = main_buffer[1];\t\t\/\/ \u30a8\u30e9\u30fc\u306e\u5834\u5408\u306b\u306f\u3053\u3053\u3092\u9055\u3046\u30c7\u30fc\u30bf\u306b\u3059\u308b\u306e\u304c\u3044\u3044\u3068\u601d\u3046\u2026TBD\r\n\t\t\t\t\t\t\t\/\/ \u30c7\u30fc\u30bf\u9577\u3092\u8a2d\u5b9a\r\n\t\t\t\t\t\t\tgvc_i2c_message->data_len = ir_data_len;\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\/\/ \u305d\u308c\u4ee5\u5916\u306a\u3089\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\/\/ \u6b63\u5e38\u306a\u30c7\u30fc\u30bf\u306f\u3042\u308a\u307e\u305b\u3093\u3001\u3068\u3059\u308b\u3079\u304d\r\n\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u304c\u7121\u3044\u65e8\u3092\u8fd4\u3059\u3001format\u3082\u6b63\u5e38\u7cfb\u3068\u5225\u3051\u308b\u3053\u3068\r\n\t\t\t\t\t\t\tsprintf(gvc_i2c_message->data, "IR DATA NONE!? ir_rx_status=%d, ir_data_len=%d, ir_mode=%d, ir_trx_flag=%d", ir_rx_status, ir_data_len, ir_mode, ir_trx_flag);\r\n\t\t\t\t\t\t\tgvc_i2c_message->data_len = strlen(gvc_i2c_message->data);\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\tsend_strdata("--- IR GET END ---");\r\n\t\t\t\t\t\tsend_crlf();\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ \u8981\u6c42\u30b3\u30de\u30f3\u30c9\u304c0x95\u306a\u3089\r\n\t\t\t\t\telse if (main_buffer[1] == 0x95)\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30e1\u30e2\u30ea\u524a\u9664\u8981\u6c42\r\n\t\t\t\t\t\tsprintf(gvc_i2c_message->data, "IR DEL");\r\n\t\t\t\t\t\tgvc_i2c_message->data_len = strlen(gvc_i2c_message->data);\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30c7\u30fc\u30bf\u524a\u9664\u30e2\u30fc\u30c9(=5)\u306b\u8a2d\u5b9a\r\n\t\t\t\t\t\tir_mode = 5;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\/\/ \u30b3\u30de\u30f3\u30c9\u30a8\u30e9\u30fc\u3092\u8a2d\u5b9a\r\n\t\t\t\t\t\tsprintf(gvc_i2c_message->data, "Unsupported %02x", temp_buffer);\r\n\t\t\t\t\t\tgvc_i2c_message->data_len = strlen(gvc_i2c_message->data);\t\t\/\/ \u30c7\u30fc\u30bf\u9577\r\n\t\t\t\t\t}\r\n\t\t\t\t\t\/\/ CRC\u3092\u8a08\u7b97\u3057\u3066\u3001\u30e1\u30c3\u30bb\u30fc\u30b8\u306e\u6700\u5f8c\u306b\u8a2d\u5b9a\r\n\t\t\t\t\tgvc_i2c_message->data[gvc_i2c_message->data_len] = GetCRC8((void *)gvc_i2c_message, GVC_I2C_MESSAGE_HEADER_SIZE + gvc_i2c_message->data_len);\r\n\t\t\t\t}\r\n\t\t\t\t\/\/ CRC\u30c1\u30a7\u30c3\u30af\u304cNG\u306a\u3089\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tsprintf(sub_buffer, "MASTER MESSAGE CRC ERROR!?");\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092+1\r\n\t\t\trx_count ++;\r\n\t\t\t\/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n\t\t\tSSP1CON1bits.CKP1 = 1;\r\n\t\t\t\/\/ \u53d7\u4fe1\u30c7\u30fc\u30bf\u304c\u30d0\u30c3\u30d5\u30a1\u3044\u3063\u3071\u3044\u306b\u306a\u3063\u305f\u308a\u3057\u305f\u3089\u30d5\u30e9\u30b0\u3067\u3082\u7acb\u3066\u3066\u30a8\u30e9\u30fc\u51e6\u7406\u3068\u304b\u3059\u308b\u3000\u2605\u5b9f\u969b\u306e\u683c\u7d0d\u4f4d\u7f6e\u306b\u6ce8\u610f\r\n\t\t\tif (rx_count >= MAIN_BUFF_SIZE)\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u6d88\u706f\r\n\t\t\t\tPORT_RESULT_LED = LED_ON;\r\n\t\t\t\trx_count = 0;\r\n\t\t\t}\r\n\t\t\t\/\/ \u305d\u308c\u4ee5\u5916\u306a\u3089\u6b63\u5e38\u3068\u3044\u3046\u3053\u3068\u3067\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u6d88\u706f\r\n\t\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t\t}\r\n\t\t}\r\n\t\t\/\/ \u30a2\u30c9\u30ec\u30b9(D\/A=0)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u53d7\u4fe1(R\/W=1)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u306b\u4f55\u304b\u3042\u308b(BF=1)\u306a\r\n\t\telse if (reg_SSP1STAT == 0b00000101)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u70b9\u706f\r\n\t\t\tPORT_RESULT_LED = LED_ON;\r\n\t\t\t\r\n\t\t\t\/\/ SSP1BUF\u3092\u7a7a\u8aad\u307f\u3057\u3066\r\n\t\t\ttemp_buffer = SSP1BUF;\r\n\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092\u521d\u671f\u5316\r\n\t\t\ttx_count = 0;\r\n\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u306e\u6700\u521d\u306e\u30c7\u30fc\u30bf\u3092SSP1BUF\u306b\u8a2d\u5b9a\r\n\t\t\tSSP1BUF = *((char *)(gvc_i2c_message) + tx_count);\r\n\t\t\t\/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n\t\t\tSSP1CON1bits.CKP1 = 1;\r\n\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092+1;\r\n\t\t\ttx_count ++;\r\n\t\t\t\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u6d88\u706f\r\n\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t}\r\n\t\t\/\/ \u30c7\u30fc\u30bf(D\/A=1)\u3067\u3001\u304b\u3064\u30de\u30b9\u30bf\u30fc\u304c\u30b9\u30ec\u30fc\u30d6\u304b\u3089\u53d7\u4fe1(R\/W=1)\u3001\u304b\u3064\u30d0\u30c3\u30d5\u30a1\u304c\u7a7a(BF=0)\u306a\u3089\r\n\t\telse if (reg_SSP1STAT == 0b00100100)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u70b9\u706f\r\n\t\t\tPORT_RESULT_LED = LED_ON;\r\n\t\t\t\r\n\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u304cGVC_I2C_MESSAGE_HEADER_SIZE\uff0b\u30c7\u30fc\u30bf\u30b5\u30a4\u30ba\uff0bCRC\u3092\u8d8a\u3048\u3066\u3044\u306a\u3044\u306a\u3089\r\n\t\t\tif (tx_count < (GVC_I2C_MESSAGE_HEADER_SIZE + gvc_i2c_message->data_len + 1))\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u306e\u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u306e\u30c7\u30fc\u30bf\u3092SSP1BUF\u306b\u8a2d\u5b9a\r\n\t\t\t\tSSP1BUF = *((char *)(gvc_i2c_message) + tx_count);\r\n\t\t\t\t\/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n\t\t\t\tSSP1CON1bits.CKP1 = 1;\r\n\t\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u3092+1;\r\n\t\t\t\ttx_count ++;\r\n\t\t\t}\r\n\t\t\t\/\/ \u305d\u3046\u3067\u306f\u306a\u304f\u3001\u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\u304cGVC_I2C_MESSAGE_HEADER_SIZE\uff0b\u30c7\u30fc\u30bf\u30b5\u30a4\u30ba\u3092\u8d85\u3048\u3066\u3044\u305f\u3089\u2026\u5909\u306a\u30c7\u30fc\u30bf\u3092\u8fd4\u3055\u306a\u3044\u3088\u3046\u306b\u3059\u308b\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t\/\/ \u30c0\u30df\u30fc\u30c7\u30fc\u30bf(NULL\u30c7\u30fc\u30bf)\u3092\u8a2d\u5b9a\u3059\u308b\r\n\t\t\t\tSSP1BUF = 0x00;\r\n\t\t\t\t\/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u30c7\u30fc\u30bf\u306e\u9001\u4fe1\u3092\u8a31\u53ef\u3059\u308b\r\n\t\t\t\tSSP1CON1bits.CKP1 = 1;\r\n\t\t\t}\r\n\t\t\t\r\n\t\t\t\/\/ \u30ea\u30b6\u30eb\u30c8LED\u3092\u6d88\u706f\r\n\t\t\tPORT_RESULT_LED = LED_OFF;\r\n\t\t}\r\n\t\t\/\/ \u3053\u308c\u3089\u4ee5\u5916\u306f\r\n\t\telse\r\n\t\t{\r\n\t\t\t\/\/ SSP1BUF\u3092\u7a7a\u8aad\u307f\u3057\u3066\r\n\t\t\ttemp_buffer = SSP1BUF;\r\n\t\t\t\/\/ SCL\u3092\u30ea\u30ea\u30fc\u30b9\u3057\u3066\u30de\u30b9\u30bf\u30fc\u306b\u6b21\u306e\u547d\u4ee4\u3092\u4fc3\u3059\r\n\t\t\tSSP1CON1bits.CKP1 = 1;\r\n\t\t}\r\n\t\t\r\n\t\tPORT_STATUS_LED = LED_OFF;\r\n\t}\r\n\t\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u30b7\u30ea\u30a2\u30eb1\u53d7\u4fe1\u5272\u308a\u8fbc\u307f\u51e6\u7406\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u30b7\u30ea\u30a2\u30eb1\u53d7\u4fe1\u5272\u308a\u8fbc\u307f(=1)\u306a\u3089 (RC1IF: EUSART1 Receive Interrupt Flag bit ... INTCON)\r\n\t\/\/ 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)\r\n\t\/\/ 0 = The EUSART1 receive buffer is empty\r\n\tif (PIR1bits.RC1IF == 1)\r\n\t{\r\n\t\t\/\/ \u30b7\u30ea\u30a2\u30eb1\u53d7\u4fe1\u5272\u308a\u8fbc\u307f\u30af\u30ea\u30a2(=0)\u2026\u306f1\u30d0\u30a4\u30c8\u53d7\u4fe1\u3059\u308c\u3070\u81ea\u52d5\u7684\u306b\u30af\u30ea\u30a2\u3055\u308c\u308b\u306e\u3067\u5fc5\u8981\u306a\u3044 \u2190 \u3046\u305d\u3001\u8981\u308b\u307f\u305f\u3044\u3001\u6642\u3005\u3061\u3083\u3093\u3068\u521d\u671f\u5316\u3057\u306a\u3044 2013.12.03 \r\n\t\tPIR1bits.RC1IF = 0;\r\n\t\t\/\/ \u53d7\u4fe1\u30b9\u30c6\u30fc\u30bf\u30b9\u3092\u53d6\u5f97\r\n\t\treg_RCSTA1 = RCSTA1;\r\n\t\t\/\/ \u53d7\u4fe1\u30b9\u30c6\u30fc\u30bf\u30b9\u3092\u78ba\u8a8d\u3057\u3066\u30d5\u30ec\u30fc\u30df\u30f3\u30b0\u30a8\u30e9\u30fc\u3001\u30aa\u30fc\u30d0\u30fc\u30e9\u30f3\u30a8\u30e9\u30fc\u304c\u306a\u3051\u308c\u3070\r\n\t\tif ((reg_RCSTA1 & 0b00000110) == 0b00000000)\r\n\t\t{\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1(RCREG1)\u304b\u30891\u30d0\u30a4\u30c8\u53d6\u5f97\r\n\t\t\tserial_rcvbuff[serial_rcvptr] = RCREG1;\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf\u3092\u52a0\u7b97(+1)\r\n\t\t\tserial_rcvptr ++;\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf\u3092\u30ea\u30f3\u30b0\u308b\r\n\t\t\tserial_rcvptr &= SERIAL_RCV_BUFFRING;\r\n\t\t}\r\n\t\t\/\/ \u53d7\u4fe1\u30b9\u30c6\u30fc\u30bf\u30b9\u3092\u78ba\u8a8d\u3057\u3066\u30aa\u30fc\u30d0\u30fc\u30e9\u30f3\u30a8\u30e9\u30fc\u304c\u3042\u308b\u306a\u3089\r\n\t\telse if (reg_RCSTA1 & 0b00000010)\r\n\t\t{\r\n\t\t\t\/\/ CREN \u30ec\u30b7\u30fc\u30d0\u30a4\u30cd\u30fc\u30d6\u30eb\u30d3\u30c3\u30c8\u3092\u30af\u30ea\u30a2\u3057\u3066\u518d\u8a2d\u5b9a\r\n\t\t\tRCSTA1bits.CREN = 0;\r\n\t\t\tRCSTA1bits.CREN = 1;\r\n\t\t}\r\n\t\t\/\/ \u30a8\u30e9\u30fc\u304c\u306a\u3044\u306a\u3089\r\n\t\telse\r\n\t\t{\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1(RCREG1)\u304b\u30891\u30d0\u30a4\u30c8\u53d6\u5f97\r\n\t\t\tserial_rcvbuff[serial_rcvptr] = RCREG1;\r\n\t\t}\r\n\t\t\r\n\t\t\/\/ \u307b\u3093\u3068\u306f\u3053\u3053\u3067\u3001\u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bfserial_rcvptr\u304c\u30ea\u30f3\u30b0\u30d0\u30c3\u30d5\u30a1\u3092\u4e0a\u66f8\u304d\u3057\u306a\u3044\u3088\u3046\u306b\r\n\t\t\/\/ \u3059\u308b\u3068\u304b\u3001\u3042\u308f\u305b\u3066\u30d5\u30ed\u30fc\u5236\u5fa1\u3059\u308b\u3068\u304b\u3001\u3044\u308d\u3044\u308d\u3042\u308b\u3051\u3069\u3001\u4eca\u56de\u306f\u3068\u308a\u3042\u3048\u305a\u307b\u3063\u3068\u304f\r\n\t}\r\n\t\r\n\t\r\n\t\/\/ \u5168\u5272\u308a\u8fbc\u307f\u3092\u8a31\u53ef(=1) (Global Interrupt Enable bit ... INTCON)\r\n\tINTCONbits.GIE = 1;\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ IR JOB RX\r\n\/\/ ------------------------------\r\nvoid ir_job_rx(void)\r\n{\r\n\t\/\/ \u6570\u79d2\u7f6e\u3044\u3066\u304b\u3089\u53d7\u4fe1\u51e6\u7406\u3092\u958b\u59cb\u3059\u308b\r\n\tDelay_10ms(100);    \/\/ 1000ms\u5f85\u3064\r\n\tDelay_10ms(100);    \/\/ 1000ms\u5f85\u3064\r\n\tDelay_10ms(100);    \/\/ 1000ms\u5f85\u3064\r\n\t\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u3092\u6271\u3046\u3068\u304d\u306b\u306f\u3001\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u3092main_buffer\u306b\u5207\u308a\u66ff\u3048\u306a\u3044\u3068\u3044\u3051\u306a\u3044\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\tir_buffer = gvc_i2c_message->data;\r\n\t\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d0\u30c3\u30d5\u30a1\u306e\u30af\u30ea\u30a2\r\n\tmemset((void *)ir_buffer, 0, IR_BUFF_SIZE);\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\u306e\u521d\u671f\u5316\r\n\tir_count = 0;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u306e\u521d\u671f\u5316\r\n\tir_bit = 1;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u5f85\u3061(1)\u306b\u8a2d\u5b9a\r\n\tir_rx_status = 1;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u540c\u4e00\u30c7\u30fc\u30bf\u30ab\u30a6\u30f3\u30bf\u3092\u521d\u671f\u5316\r\n\tir_same_count = 0;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9577\u3092\u521d\u671f\u5316\r\n\tir_data_len = 0;\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u958b\u59cb\u3092\u9001\u4fe1\r\n\tsend_strdata("--- IR RX START ---");\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u52d5\u4f5c\u30d5\u30e9\u30b0\u3092\u53d7\u4fe1\u958b\u59cb\u306b\u8a2d\u5b9a\r\n\tir_trx_flag = 1;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u8aad\u307f\u53d6\u308a\u30bf\u30a4\u30e0\u30a2\u30a6\u30c8\u30bf\u30a4\u30de\u30fc\u30b9\u30bf\u30fc\u30c8\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc0\u30ab\u30a6\u30f3\u30bf\u3092\u521d\u671f\u5316\r\n\ttimer0_count = 0;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\tTMR0H = timer0_h;\r\n\tTMR0L = timer0_l;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u521d\u671f\u5316\r\n\tINTCONbits.TMR0IF = 0;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc0\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Timer0 Overflow Interrupt Enable bit ... INTCON)\r\n\tINTCONbits.TMR0IE = 1; \r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u958b\u59cb!!\r\n\tT0CON |= 0b10000000;\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u3053\u3053\u307e\u3067\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30b9\u30c6\u30fc\u30bf\u30b9LED\u70b9\u706f\r\n\tPORT_STATUS_LED = LED_ON;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u53d7\u4fe1\u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u30bf\u30a4\u30de\u30fc\u30b9\u30bf\u30fc\u30c8\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30ab\u30a6\u30f3\u30bf\u3092\u521d\u671f\u5316\r\n\ttimer1_count = 0;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\tTMR1H = timer1_h;\r\n\tTMR1L = timer1_l;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u521d\u671f\u5316\r\n\tPIR1bits.TMR1IF = 0;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Timer1 Overflow Interrupt Enable bit ... PIE1)\r\n\tPIE1bits.TMR1IE = 1; \r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u958b\u59cb!!\r\n\tT1CON |= 0b00000001;\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u4e2d\u306f\u30eb\u30fc\u30d7\r\n\twhile (ir_trx_flag == 1)\r\n\t{\r\n\t\tDelay_10ms(1);    \/\/ 10ms\u5f85\u3064 \u2190\u5927\u4e8b\u3001\u5224\u5b9a\u7528\u306e\u30d5\u30e9\u30b0\u30ec\u30b8\u30b9\u30bf\u3092\u7834\u58ca\u3057\u306a\u3044\u3088\u3046\u306b\u30a6\u30a7\u30a4\u30c8\u5165\u308c\u306a\u3044\u3068\u30c0\u30e1 2013.12.03\r\n\t}\r\n\t\r\n\tsend_strdata("ir_trx_flag = ");\r\n\tsend_intdata(ir_trx_flag);\r\n\tsend_crlf();\r\n\tsend_strdata("IR COUNT = ");\r\n\tsend_intdata(ir_count);\r\n\tsend_crlf();\r\n\tsend_strdata("DATA LENGTH = ");\r\n\tsend_intdata(ir_data_len);\r\n\tsend_crlf();\r\n\t\t\t\t\r\n\tsend_strdata("--- IR RX END ---");\r\n\tsend_crlf();\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ IR JOB TX\r\n\/\/ ------------------------------\r\nvoid ir_job_tx(void)\r\n{\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\tir_buffer = gvc_i2c_message->data;\r\n\t\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u4f4d\u7f6e\u306e\u521d\u671f\u5316\r\n\tir_count = 0;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\u306e\u521d\u671f\u5316\r\n\tir_bit = 1;\r\n\t\/\/ \u521d\u56de\u306e\u9001\u4fe1\u30d3\u30c3\u30c8\u3092\u8a2d\u5b9a(\u9001\u4fe1\u30d0\u30a4\u30c8\u3068\u9001\u4fe1\u5bfe\u8c61\u30d3\u30c3\u30c8\u3092AND\u3057\u305f\u5024)\r\n\tir_tx_data = *ir_buffer & ir_bit;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u4fe1\u30c7\u30fc\u30bf\u306e\u6700\u5f8c\u3092\u8a2d\u5b9a\r\n\tir_buffer_end = ir_buffer + ir_data_len;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0\u3092\u9001\u4fe1\u4e2d(=2)\u306b\u8a2d\u5b9a\r\n\tir_trx_flag = 2;\r\n\t\/\/ \u8d64\u5916\u7dda\u9001\u4fe1\u56de\u6570\u3092\u521d\u671f\u5316\r\n\tir_tx_count = 1;\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u958b\u59cb\u3092\u9001\u4fe1\r\n\tsend_strdata("--- IR TX START ---");\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u6570\u3092\u9001\u4fe1\r\n\tsend_strdata("DATA LENGTH = ");\r\n\tsend_intdata(ir_data_len);\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u7d50\u679c\u3092\u9001\u4fe1\r\n\tsend_strdata("STATUS = ");\r\n\tsend_intdata(ir_rx_status);\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u9001\u4fe1\u958b\u59cbLED\u70b9\u706f\r\n\tPORT_RESULT_LED = LED_ON;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9001\u4fe1\u7528PWM\u30b9\u30bf\u30fc\u30c8\r\n\t\/\/ ------------------------------\r\n\t\/\/ PSTR1CON \u3092\u8a2d\u5b9a(\u505c\u6b62)\r\n\tPSTR1CON = 0b00010000;\t\/\/ STR1SYNC = 1, STR1A = 0;\r\n\t\/\/ PWM\u306e\u5468\u671f\u3092\u8a2d\u5b9a(\u8a73\u3057\u304f\u306f\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u53c2\u7167)\r\n\tPR2 = 104;\r\n\t\/\/ PWM\u306e\u30c7\u30e5\u30fc\u30c6\u30a3\u6bd4\u3092\u8a2d\u5b9a(\u8a73\u3057\u304f\u306f\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u53c2\u7167)\r\n\tCCPR1L = 0b00100011;\r\n\tCCP1CON = 0b00111100;\r\n\t\/\/ PWM\u306e\u521d\u671f\u5024\u3092\u8a2d\u5b9a(\u8a73\u3057\u304f\u306f\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u53c2\u7167)\r\n\tTMR2 = 104;\r\n\t\/\/ PWM\u7528\u30bf\u30a4\u30de\u30fc(TIMER2)\u3092\u30b9\u30bf\u30fc\u30c8(\u8a73\u3057\u304f\u306f\u30c7\u30fc\u30bf\u30b7\u30fc\u30c8\u53c2\u7167)\r\n\tT2CON |= 0b00000100;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9001\u4fe1\u7528\u30bf\u30a4\u30de\u30fc\u30b9\u30bf\u30fc\u30c8\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u30ab\u30a6\u30f3\u30bf\u3092\u521d\u671f\u5316\r\n\ttimer1_count = 0;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5024\u8a2d\u5b9a\r\n\tTMR1H = timer1_h;\r\n\tTMR1L = timer1_l;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u30d5\u30e9\u30b0\u521d\u671f\u5316\r\n\tPIR1bits.TMR1IF = 0;\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc1\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Timer1 Overflow Interrupt Enable bit ... PIE1)\r\n\tPIE1bits.TMR1IE = 1; \r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5272\u308a\u8fbc\u307f\u958b\u59cb!!\r\n\tT1CON |= 0b00000001;\r\n\t\r\n\t\/\/ \u9001\u4fe1\u4e2d\u306f\u30eb\u30fc\u30d7\r\n\twhile (ir_trx_flag == 2)\r\n\t{\r\n\t\tDelay_10ms(1);    \/\/ 10ms\u5f85\u3064 \u2190\u5927\u4e8b\u3001\u5224\u5b9a\u7528\u306e\u30d5\u30e9\u30b0\u30ec\u30b8\u30b9\u30bf\u3092\u7834\u58ca\u3057\u306a\u3044\u3088\u3046\u306b\u30a6\u30a7\u30a4\u30c8\u5165\u308c\u306a\u3044\u3068\u30c0\u30e1 2013.12.03\r\n\t}\r\n\t\r\n\tsend_strdata("--- IR TX END ---");\r\n\tsend_crlf();\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ IR JOB SEND to Serial\r\n\/\/ ------------------------------\r\nvoid ir_job_send(void)\r\n{\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\tir_buffer = gvc_i2c_message->data;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u8aad\u307f\u53d6\u308a\u30c7\u30fc\u30bf\u3092\u30b7\u30ea\u30a2\u30eb\u3067\u9001\u4fe1\r\n\t\/\/ ------------------------------\r\n\tsend_strdata("--- IR SEND SERIAL ---");\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u30b5\u30f3\u30d7\u30ea\u30f3\u30b0\u6570\u3092\u9001\u4fe1\r\n\tsend_strdata("DATA LENGTH = ");\r\n\tsend_intdata(ir_data_len);\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u7d50\u679c\u3092\u9001\u4fe1\r\n\tsend_strdata("STATUS = ");\r\n\tsend_intdata(ir_rx_status);\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u9001\u4fe1\u51e6\u7406\r\n\tsend_ir_rxdata();\r\n\t\r\n\tsend_strdata("--- IR SEND END ---");\r\n\tsend_crlf();\r\n}\r\n\r\n\/\/ ------------------------------\r\n\/\/ IR JOB DELETE\r\n\/\/ ------------------------------\r\nvoid ir_job_delete(void)\r\n{\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3057\u3066\u6539\u3081\u3066\u8a2d\u5b9a\u3059\u308b\r\n\tir_buffer = gvc_i2c_message->data;\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u8aad\u307f\u53d6\u308a\u30c7\u30fc\u30bf\u3092\u30b7\u30ea\u30a2\u30eb\u3067\u9001\u4fe1\r\n\t\/\/ ------------------------------\r\n\tsend_strdata("--- IR DELETE START---");\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b\u3092\u53d7\u4fe1\u30c7\u30fc\u30bf\u306a\u3057(0)\u306b\u3059\u308b\r\n\tir_rx_status = 0;\r\n\t\/\/ \u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u306e\u30c7\u30fc\u30bf\u9577\u3092\u30af\u30ea\u30a2\r\n\tir_data_len = 0;\r\n\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d0\u30c3\u30d5\u30a1\u306e\u30af\u30ea\u30a2\r\n\tmemset((void *)ir_buffer, 0, IR_BUFF_SIZE);\r\n\t\/\/ \u5f85\u907f\u30d0\u30c3\u30d5\u30a1\u3082\u30af\u30ea\u30a2\r\n\tmemset((void *)ir_saved_buffer, 0, sizeof(ir_saved_buffer));\r\n\t\r\n\tsend_strdata("--- IR DELETE END---");\r\n\tsend_crlf();\r\n}\r\n\r\n\r\n\/\/ --------------------------------------------------\r\n\/\/ Main loop\r\n\/\/ --------------------------------------------------\r\nvoid main(void)\r\n{\r\n\tchar rcv_data;\t\t\t\t\t\t\t\/\/ \u53d7\u4fe1\u30c7\u30fc\u30bf\r\n\t\r\n\t\/\/ Setup 18F26K22\r\n\tinit_pic_18F26K22();\r\n\t\r\n\t\/\/ Setup MSSP1 18F26K22\r\n\tinit_mssp1_18F26K22();\r\n\t\r\n\t\/\/ Setup EUSART 18F26K22\r\n\tinit_eusart_18F26K22();\r\n\t\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u3053\u308c\u3088\u308a\u4e0b\u306b\u3001\u500b\u5225\u306e\u8a2d\u5b9a\u3092\u8a18\u8ff0\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ LED Brink\r\n\tled_brink(1);\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc3\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit 7-6 : TMRxCS<1:0>: Timer1\/3\/5 Clock Source Select bits\r\n\t\/\/     11 =Reserved. Do not use.\r\n\t\/\/     10 =Timer1\/3\/5 clock source is pin or oscillator:\r\n\t\/\/         If TxSOSCEN = 0:\r\n\t\/\/             External clock from TxCKI pin (on the rising edge)\r\n\t\/\/         If TxSOSCEN = 1:\r\n\t\/\/             Crystal oscillator on SOSCI\/SOSCO pins\r\n\t\/\/     01 =Timer1\/3\/5 clock source is system clock (FOSC)\r\n\t\/\/     00 =Timer1\/3\/5 clock source is instruction clock (FOSC\/4)\r\n\t\/\/ bit 5-4 : TxCKPS<1:0>: Timer1\/3\/5 Input Clock Prescale Select bits\r\n\t\/\/     11 = 1:8 Prescale value\r\n\t\/\/     10 = 1:4 Prescale value\r\n\t\/\/     01 = 1:2 Prescale value\r\n\t\/\/     00 = 1:1 Prescale value\r\n\t\/\/ bit 3   : TxSOSCEN: Secondary Oscillator Enable Control bit\r\n\t\/\/     1 = Dedicated Secondary oscillator circuit enabled\r\n\t\/\/     0 = Dedicated Secondary oscillator circuit disabled\r\n\t\/\/ bit 2   : TxSYNC: Timer1\/3\/5 External Clock Input Synchronization Control bit\r\n\t\/\/     TMRxCS<1:0> = 1X\r\n\t\/\/         1 = Do not synchronize external clock input\r\n\t\/\/         0 = Synchronize external clock input with system clock (FOSC)\r\n\t\/\/     TMRxCS<1:0> = 0X\r\n\t\/\/         This bit is ignored. Timer1\/3\/5 uses the internal clock when TMRxCS<1:0> = 1X.\r\n\t\/\/ bit 1   : TxRD16: 16-Bit Read\/Write Mode Enable bit\r\n\t\/\/     1 = Enables register read\/write of Timer1\/3\/5 in one 16-bit operation\r\n\t\/\/     0 = Enables register read\/write of Timer1\/3\/5 in two 8-bit operation\r\n\t\/\/ bit 0   : TMRxON: Timer1\/3\/5 On bit\r\n\t\/\/     1 = Enables Timer1\/3\/5\r\n\t\/\/     0 = Stops Timer1\/3\/5\r\n\t\/\/     Clears Timer1\/3\/5 Gate flip-flop\r\n\tT3CON = 0b00100010;\t\t\t\/\/ FOSC\/4, 1:4, disabled, ignored, 16bit, Timer Stop\r\n\t\r\n\t\/\/ ------------------------------\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc3\u30b2\u30fc\u30c8\u5236\u5fa1\u30ec\u30b8\u30b9\u30bf\u8a2d\u5b9a\r\n\t\/\/ ------------------------------\r\n\t\/\/ bit 7 TMRxGE: Timer1 Gate Enable bit\r\n\t\/\/     If TMRxON = 0:\r\n\t\/\/         This bit is ignored\r\n\t\/\/     If TMRxON = 1:\r\n\t\/\/         1 = Timer1 counting is controlled by the Timer1 gate function\r\n\t\/\/         0 = Timer1 counts regardless of Timer1 gate function\r\n\t\/\/ bit 6 T1GPOL: Timer1 Gate Polarity bit\r\n\t\/\/     1 = Timer1 gate is active-high (Timer1 counts when gate is high)\r\n\t\/\/     0 = Timer1 gate is active-low (Timer1 counts when gate is low)\r\n\t\/\/ bit 5 T1GTM: Timer1 Gate Toggle Mode bit\r\n\t\/\/     1 = Timer1 Gate Toggle mode is enabled\r\n\t\/\/     0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared\r\n\t\/\/     Timer1 gate flip-flop toggles on every rising edge.\r\n\t\/\/ bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit\r\n\t\/\/     1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate\r\n\t\/\/     0 = Timer1 gate Single-Pulse mode is disabled\r\n\t\/\/ bit 3 T1GGO\/DONE: Timer1 Gate Single-Pulse Acquisition Status bit\r\n\t\/\/     1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge\r\n\t\/\/     0 = Timer1 gate single-pulse acquisition has completed or has not been started\r\n\t\/\/     This bit is automatically cleared when T1GSPM is cleared.\r\n\t\/\/ bit 2 T1GVAL: Timer1 Gate Current State bit\r\n\t\/\/     Indicates the current state of the Timer1 gate that could be provided to TMRxH:TMRxL.\r\n\t\/\/     Unaffected by Timer1 Gate Enable (TMRxGE).\r\n\t\/\/ bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits\r\n\t\/\/     00 = Timer1 Gate pin\r\n\t\/\/     01 = Timer0 overflow output\r\n\t\/\/     10 = Comparator 1 optionally synchronized output (SYNCC1OUT)\r\n\t\/\/     11 = Comparator 2 optionally synchronized output (SYNCC2OUT)(1)\r\n\tT3GCON = 0b00000000;\t\t\/\/ ignored, active-low, disabled, disabled ...\r\n\t\r\n\t\/\/ Setup 18F26K22 for Analog Voltage\r\n\tinit_pic_for_analogvoltage();\r\n\t\r\n\t\/\/ Get Vdd Voltage\r\n\tvdd_volt = get_vdd();\r\n\t\/\/ \u3082\u3057Vdd\u304c4.0V\u3088\u308a\u5927\u304d\u3044\u3068\u304b\u30011.0V\u672a\u6e80\u306a\u3089\r\n\tif (vdd_volt > 4.0 || vdd_volt < 1.0)\r\n\t{\r\n\t\t\/\/ \u305f\u3076\u3093\u3061\u3083\u3093\u3068\u6e2c\u5b9a\u3067\u304d\u3066\u3044\u306a\u3044\u3063\u3066\u3053\u3068\u3067\u30015.00\u306b\u56fa\u5b9a\r\n\t\tvdd_volt = 5.00;\r\n\t}\r\n\t\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u3092I2C\u30e1\u30c3\u30bb\u30fc\u30b8\u30dd\u30a4\u30f3\u30bf\u306b\u8a2d\u5b9a\r\n\tgvc_i2c_message = (GVC_I2C_MESSAGE_t *)main_buffer;\r\n\t\/\/ \u30e1\u30a4\u30f3\u30d0\u30c3\u30d5\u30a1\u306edata[]\u30dd\u30a4\u30f3\u30bf\u3092ir_buffer\u3068\u3059\u308b\r\n\tir_buffer = gvc_i2c_message->data;\r\n\t\r\n\t\/\/ \u5404\u7a2e\u30b0\u30ed\u30fc\u30d0\u30eb\u5909\u6570\u306e\u521d\u671f\u5316\u2026\u30b0\u30ed\u30fc\u30d0\u30eb\u5909\u6570\u306f\u5ba3\u8a00\u6642\u306b\u521d\u671f\u5316\u3057\u3066\u3044\u3066\u3082\u5b9f\u969b\u306b\u306f\u3057\u3066\u304f\u308c\u306a\u3044\u2026orz 2013.07.11 T.Kabu\r\n\trx_count = 0;\t\t\t\t\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\r\n\ttx_count = 0;\t\t\t\t\t\t\t\/\/ \u9001\u4fe1\u30d0\u30c3\u30d5\u30a1\u4f4d\u7f6e\r\n\ti2c_status = 0;\t\t\t\t\t\t\t\/\/ I2C\u30b9\u30c6\u30fc\u30bf\u30b9 0:\u5f85\u6a5f\u72b6\u614b 1:\u30c7\u30fc\u30bf\u53d7\u4fe1\u4e2d 10:\u30c7\u30fc\u30bf\u53d7\u4fe1\u5b8c\u4e86\r\n\tir_mode = 0;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30b8\u30e5\u30fc\u30eb\u52d5\u4f5c\u30e2\u30fc\u30c9(0=\u53d7\u4fe1\u30c7\u30fc\u30bf\u304c\u3042\u308c\u3070\u518d\u9001\u4fe1\u30011=\u8aad\u307f\u53d6\u308a)\r\n\tir_rxmax = 0;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u6700\u5927\u53d7\u4fe1\u30e2\u30fc\u30c9(0=\u901a\u5e38\u30011=\u6700\u5927)\r\n\tir_data = 0;\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\r\n\/\/\tir_status = LED_OFF;\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u3072\u3068\u3064\u524d\u306e\u72b6\u614b\r\n\tir_status = PORT_IR_RX;\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u306e\u3072\u3068\u3064\u524d\u306e\u72b6\u614b\r\n\tir_bit = 1;\t\t\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30d3\u30c3\u30c8\u4f4d\u7f6e\r\n\tir_trx_flag = 0;\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u9001\u53d7\u4fe1\u30d5\u30e9\u30b0(0=none, 1=\u53d7\u4fe1\u4e2d, 2=\u9001\u4fe1\u4e2d)\r\n\tir_rx_status = 0;\t\t\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u72b6\u614b(0=none, 1=RXwait,2=RXing etc...)\r\n\t\r\n\t\/\/ \u30bf\u30a4\u30de\u30fc\u5024\u3092\u521d\u671f\u5316\r\n\tinit_timer_18F26K22();\r\n\r\n\t\/\/ ----------------------------------------\r\n\t\/\/ \u500b\u5225\u8a2d\u5b9a\u7d42\u4e86\r\n\t\/\/ ----------------------------------------\r\n\t\r\n\t\/\/ LED Brink\r\n\tled_brink(2);\r\n\t\r\n\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u30dd\u30a4\u30f3\u30bf\u3092\u521d\u671f\u5316\r\n\tserial_rcvptr = 0;\r\n\t\/\/ \u53d7\u4fe1\u8aad\u307f\u51fa\u3057\u30dd\u30a4\u30f3\u30bf\u3092\u521d\u671f\u5316\r\n\tserial_readptr = 0;\r\n\t\r\n\t\/\/ \u30d0\u30c3\u30d5\u30a1\u3092\u521d\u671f\u5316\r\n\/\/\/\tmemset((void *)serial_rcvbuff, 0x00, sizeof(serial_rcvbuff));\r\n\tmemset((void *)main_buffer, 0x00, sizeof(main_buffer));\r\n\tmemset((void *)sub_buffer, 0x00, sizeof(sub_buffer));\r\n\t\r\n\t\/\/ EUSART1 RX \u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (EUSART1 Receive Interrupt Enable bit ... PIE1)\r\n\tPIE1bits.RC1IE = 1;\r\n\t\/\/ MSSP\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Synchronous Serial Port (MSSP) Interrupt Enable bit ... PIE1)\r\n\tPIE1bits.SSP1IE = 1;\r\n\t\/\/ \u5468\u8fba\u5272\u308a\u8fbc\u307f\u8a31\u53ef(=1) (Peripheral Interrupt Enable bit ... INTCON)\r\n\tINTCONbits.PEIE = 1;\r\n\t\/\/ \u5168\u5272\u308a\u8fbc\u307f\u3092\u8a31\u53ef(=1) (Global Interrupt Enable bit ... INTCON)\r\n\tINTCONbits.GIE = 1;\r\n\t\r\n\t\/\/ \u30d0\u30fc\u30b8\u30e7\u30f3\u3092\u9001\u4fe1\r\n\tsend_strdata(VERSION);\r\n\tsend_crlf();\r\n\t\r\n\t\/\/ LED Brink\r\n\tled_brink(3);\r\n\t\r\n\t\/\/ \u30e1\u30a4\u30f3\u30eb\u30fc\u30d7\r\n\twhile(1)\r\n\t{\r\n\t\t\r\n\t\t\/\/ \u30b7\u30ea\u30a2\u30eb\u30d0\u30c3\u30d5\u30a1\u306b\u672a\u8aad\u30c7\u30fc\u30bf\u304c\u306a\u3044\u306a\u3089\u30b9\u30eb\u30fc\r\n\t\tif (serial_rcvptr == serial_readptr)\r\n\t\t{\r\n\t\t}\r\n\t\t\/\/ \u3042\u308b\u306a\u3089\r\n\t\telse\r\n\t\t{\r\n\t\t\t\/\/ \u53d7\u4fe1\u30d0\u30c3\u30d5\u30a1\u304b\u3089\u4e00\u6587\u5b57\u53d6\u5f97\r\n\t\t\trcv_data = rcv_serialdata();\r\n\t\t\t\r\n\t\t\t\/\/ R\u304c\u6765\u305f\u3089\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u8aad\u307f\u53d6\u308a\u30e2\u30fc\u30c9\u306b\u3059\u308b\r\n\t\t\tif (rcv_data == 'R')\r\n\t\t\t{\r\n\t\t\t\tsend_strdata("R recieved.");\r\n\t\t\t\tsend_crlf();\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u30e2\u30fc\u30c9\u3092\u901a\u5e38(=0)\u306b\r\n\t\t\t\tir_rxmax = 0;\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u8aad\u307f\u53d6\u308a\u30e2\u30fc\u30c9(=1)\u306b\r\n\t\t\t\tir_mode = 1;\r\n\t\t\t}\r\n\t\t\t\/\/ M\u304c\u6765\u305f\u3089\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u6700\u5927\u8aad\u307f\u53d6\u308a\u30e2\u30fc\u30c9\u306b\u3059\u308b\r\n\t\t\telse if (rcv_data == 'M')\r\n\t\t\t{\r\n\t\t\t\tsend_strdata("M recieved.");\r\n\t\t\t\tsend_crlf();\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u30e2\u30fc\u30c9\u3092\u6700\u5927(=1)\u306b\r\n\t\t\t\tir_rxmax = 1;\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u8aad\u307f\u53d6\u308a\u30e2\u30fc\u30c9(=1)\u306b\r\n\t\t\t\tir_mode = 1;\r\n\t\t\t}\r\n\t\t\t\/\/ T\u304c\u6765\u305f\u3089\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u9001\u4fe1\u30e2\u30fc\u30c9\u306b\u3059\u308b\r\n\t\t\telse if (rcv_data == 'T')\r\n\t\t\t{\r\n\t\t\t\tsend_strdata("T recieved.");\r\n\t\t\t\tsend_crlf();\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u518d\u9001\u4fe1\u30e2\u30fc\u30c9(=2)\u306b\r\n\t\t\t\tir_mode = 2;\r\n\t\t\t}\r\n\t\t\t\/\/ S\u304c\u6765\u305f\u3089\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u30b7\u30ea\u30a2\u30eb\u51fa\u529b\u30e2\u30fc\u30c9\u306b\u3059\u308b\r\n\t\t\telse if (rcv_data == 'S')\r\n\t\t\t{\r\n\t\t\t\tsend_strdata("S recieved.");\r\n\t\t\t\tsend_crlf();\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30b7\u30ea\u30a2\u30eb\u51fa\u529b\u30e2\u30fc\u30c9(=3)\u306b\r\n\t\t\t\tir_mode = 3;\r\n\t\t\t}\r\n\t\t\t\/\/ D\u304bC\u304c\u6765\u305f\u3089\u8d64\u5916\u7dda\u30c7\u30fc\u30bf\u3092\u524a\u9664\u3059\u308b\r\n\t\t\telse if (rcv_data == 'D')\r\n\t\t\t{\r\n\t\t\t\tsend_strdata("D recieved.");\r\n\t\t\t\tsend_crlf();\r\n\t\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30c7\u30fc\u30bf\u524a\u9664\u30e2\u30fc\u30c9(=5)\u306b\r\n\t\t\t\tir_mode = 5;\r\n\t\t\t}\r\n\t\t}\r\n\t\t\/\/ \u3082\u3057\u30ea\u30e2\u30b3\u30f3(\u6700\u5927)\u8aad\u307f\u53d6\u308a\u30e2\u30fc\u30c9\u306a\u3089\r\n\t\tif (ir_mode == 1)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u53d7\u4fe1\u51e6\u7406\r\n\t\t\tir_job_rx();\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30b7\u30ea\u30a2\u30eb\u9001\u4fe1\u51e6\u7406\r\n\t\t\tir_job_send();\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30af\u30ea\u30a2\r\n\t\t\tir_mode = 0;\r\n\t\t}\r\n\t\t\/\/ \u3082\u3057\u30ea\u30e2\u30b3\u30f3\u518d\u9001\u4fe1\u30e2\u30fc\u30c9\u306a\u3089\r\n\t\tif (ir_mode == 2)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u518d\u9001\u4fe1\u51e6\u7406\r\n\t\t\tir_job_tx();\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30af\u30ea\u30a2\r\n\t\t\tir_mode = 0;\r\n\t\t}\r\n\t\t\/\/ \u3082\u3057\u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u51fa\u529b\u30e2\u30fc\u30c9\u306a\u3089\r\n\t\tif (ir_mode == 3)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u30b7\u30ea\u30a2\u30eb\u9001\u4fe1\u51e6\u7406\r\n\t\t\tir_job_send();\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30af\u30ea\u30a2\r\n\t\t\tir_mode = 0;\r\n\t\t}\r\n\t\t\/\/ \u3082\u3057\u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u524a\u9664\u30e2\u30fc\u30c9\u306a\u3089\r\n\t\tif (ir_mode == 5)\r\n\t\t{\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30c7\u30fc\u30bf\u524a\u9664\u51e6\u7406\r\n\t\t\tir_job_delete();\r\n\t\t\t\/\/ \u30ea\u30e2\u30b3\u30f3\u30e2\u30fc\u30c9\u3092\u30af\u30ea\u30a2\r\n\t\t\tir_mode = 0;\r\n\t\t}\r\n\t}\r\n}\r\n<\/pre>\n","protected":false},"excerpt":{"rendered":"
\/\/ ————————————————– \/\/ Global Versatile Controler http:\/\/www.gvc-on.net\/ \/\/  … \u7d9a\u304d\u3092\u8aad\u3080 →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":622,"menu_order":33,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-644","page","type-page","status-publish","hentry"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/644","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=644"}],"version-history":[{"count":2,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/644\/revisions"}],"predecessor-version":[{"id":655,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/644\/revisions\/655"}],"up":[{"embeddable":true,"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=\/wp\/v2\/pages\/622"}],"wp:attachment":[{"href":"https:\/\/www.gvc-on.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=644"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}